clock signal termination

[circuit]

clock termination

I am designing a board which takes in a external clock through a SMA connector, Now I was wondering what should be the width of the clock trace (10mils) ? and what should be the termination on the the signal ? The clock frequency will be a max of about 19 Mhz.

I am attatching the circuit where I need to route the input clock to two different chips...What should be the R, C values and what if there is just one clock I am going to route directly to the chip ( should I choose 50 ohms in this case ?) Thanks much. Where should the R be placed ?

 

[jdhar]

signal termination

are you using 50 ohm traces?

 

[rfmw]

What is the max clock PCB trace length? What is the rise/fall time of the clock signal? Is it a sinewave? 19 MHz is too low frequency to even bother with termination, except if you're dealing with high-speed (GHz capable) logic...

 

[IanP]

how to route a clock signal on a pc board

Assuming that the clock signal is comming from "not far away" (≈500mm of coax) I would not bother with any terminations, such as R, RC ...
Keep in mind that connecting 50Ω termination resistor will draw ≈100mA (peak) current from 0-5V clock signal.

What yo may consider is to use one buffer gate close to SMA connector (with ≈4.7k resistor tied up to +V) and then running this already buffered clock signal to other gates on the PCB ..

 

[circuit]

how route signal clock pcb

yeah I am using 50 ohm traces. The clock signals trace (from the SMA connector to the device pin) is around 1 inch on the board and it will be definitely less than 500 mm through the coaxial cable....I am not going to operate the board at anything greater than 20 MHz.

And I had seen this circuit on one of Analog Devices evaluation board and the clock frequency here is 50 MHz. they seem to have a termination resistor in their circuit ? Also what I found on the board layout is they route the clock on the 1st layer till the input of the gate and then the output they route on the 4th layer even though there is enough space on the 1st layer to the pin. I was wondering why they do that ?

 

[IanP]

clock terminations

It looks like this circuit takes a sinewave(or similar) and converts it to CMOS square wave clock signal. I don't think you need anything like that.

As to your other question, I would't be surprised if they used one of tese bloody auto-routers programs ..

 

[circuit]

high speed clock termination

Oh okay thanks... So when do we consider termination of signals ( in a broad sense ) ?

I just came across this through google

Regardless of the clock or data frequency the design uses, the Effective Operating Frequency of a circuit, or trace is: Signal Frequency [GHz] = [0.35] / [Signal Transition Time {nSec}]. For signal Transition time, use the shorter value of Tr [Rise Time] or Tf [Fall Time]. For example: a design that uses a signal period of 50MHz with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz ~ which is far above the actual operating frequency [Period] of the signal. The FreqKnee = 0.5/Tr, the frequency at which most of the energy resides below.

PWB traces [or cables] should be terminated (using one of the schemes listed below) when the trace length exceeds the following: Length > tr / [ 2 x t pr ]Where tr = Signal rise time, t pr = Signal propagation rate
For a general approximation this page uses: 150ps/inch for FR4 [Board Material], and 130pS/inch for Polimide [Board Material]. For example, using FR4 [150ps/inch] a trace with a 1.1nS rise time would need to be terminated if it exceeded 3.3 inches

 

[IanP]

external clock termination

PCB TRACE GENERAL GUIDELINES
• To maximize signal integrity, the use of controlled impedance traces of Z0
= 50 ohms (±10%) characteristic impedance should be considered.
• Consider routing high frequency signals on layers adjacent to a common
reference plane (i.e. power or ground).
• Route each data group (DQS and DQ) on the same layer to match
propagation delays and minimize skew.
• Route similar signals (i.e. address bus or data bus) on the same layer to
match propagation delays and minimize signal –signal skew.
• Separate low frequency and high frequency signals to minimize crosstalk.
• Traces should be routed in a daisy chain manner versus a star topology
to maintain signal integrity and facilitate a termination connection (if
required).

Averything above is true, but this guideline describes situation with data throughput rates of >5-10Gbps.
Below is another example of clock termination on a PCB .. but again, it was implemented in >1GHz system ..

I dont want to use any particular cut-off frequency above which you will use 50Ω terminations .. let common sense prevail ..

So, 20MHz, 50MHz, .. 100MHz if you really want to, you can place two 1kΩ resistors, one between signal and 0V, and one between signal and +5V, but I don't think it is necessary ..

 

[jdhar]

best termination for clock signals

In Johnson's book, he recommends using some sort of termination scheme when the trace length will be longer than 1/6th the electrical length, which is the signals rise time divided by propagation speed (~150ps/inch in FR4). ]

 

[newbie101]

clock data termination

why not ( (R1+Xc2) // Zin ) = 50Ω

( since 50Ω is characteristic impedance of line )
where Xc2 is impedance of C2 at clock frequency
and Zin is the imput impedance of U3

similar for the other branch

is this too simplistic a view of the situation?

regards,
newbie

 

[binu G]

signals termination

hi,
if i have a multiple frequency selection for a particular tracks what parameters i have to concider.
eg.
i have a link port which can work in different frequency slot.
what measures should be taken regarding this issue.

Regards
Binu George

 

[circuit]

10 inch 20mhz pcb trace

if i just need to route a main clock and then make a Y and route the two clock to the buffers, has there got to be any change in the trace width of Y ?

ex,
-----------------------clk1
|
|
MCLK
|
|
--------------------------clk2

if the trace width of MCLK is 10 mils, ( appx 50 ohm trace) then each of the traces clk1 and clk2 also needs to be 10 mils ?

there are no transmission line effects here in my system since I am dealing with low frequency/rise times... thanks much !

 

[newbie101]

star clock termination

1)change to 5 mils for the branches so there will be no impedance change

2)also since youre branching, there will be reflection depending on how you draw the traces at the junction... ( im not sure which junction shape would be best to avoid reflection )