Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

clock signal generation

Status
Not open for further replies.
F

fly1

Newbie level 6
Newbie level 6
Joined
Sep 1, 2013
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
67
how to generate a clock signal in cadence?
do i have to create a clock signal generator for that?
 

analoglib/vpulse, set parameters to suit. If you are talking
about analog / mixed signal design.
 
  • Like
Reactions: fly1

    F

    fly1

    Points: 2
    Helpful Answer Positive Rating
how to generate a clock signal in cadence?
do i have to create a clock signal generator for that?
Click to expand...

Hi fly1

The best ways are introduced by dick_freebird . but if you are attempting to make it via a circuit ( in cadence ) you can simply use a not gate and just an RC network .
Best Wishes
Goldsmith
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top