Clock sharing among 2 SMPS LTC's controllers

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andre_luis

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Hello,

I'm designing two SMPS with the Linear Technologies' LTPowerCAD tool,set; by the way a very interesting platform.
Due to specific constraints I will not be able to use a single SMPS with multiple output derivations.

However, unlike the Texas platform I used earlier, this one doesn't provide an option to use the same CLK from one chip to another; I mean, despite marked the option for that, in the diagram generated for simulation in LTSpice it is not clear how to do this; in fact, even the controller datasheet doesn't makes it clear how to do this. I'm using the LTC3891 as a 5v converter for the control logic and the LTC3777 for the Power.

Does anyone have any information or a link on how to proceed with this oscillator clock sharing?
 

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The datasheets specify a feature to synchronize to external clock, but the devices don't provide a clock output for chaining. Under circumstances, the output node can be used for sync purposes, but only if it never stops switching. In the general case, you'll use a separate oscillator.
 

    andre_luis

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Hi,

you could use an external clock generator and feed both regulator´s PLLIN with the clock.
I expect a benefit if you feed one chip with an inverted clock.

Klaus
 
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FvM said:
The datasheets specify a feature to synchronize to external clock, but the devices don't provide a clock output for chaining
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This is a pitfull overlook from the manufacturer, as the power supply for the entire circuit is taken precisely from this SMPS, so an extra power supply would be needed to power this oscillator. Thanks for the insight.
 

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The SMPS doesn't necessarily need the external oscillator at startup. So it can well supply the oscillator, e.g. a 555.
 

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FvM said:
The SMPS doesn't necessarily need the external oscillator at startup. So it can well supply the oscillator, e.g. a 555.
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I got, so once the necessary startup timing has elapsed to supply the 555, I should switch the input signal from the
PLLIN/MODE pin of the VCC to the CLK, is it? Anyway, this CLK could be available at some output pin, albeit programmable -
it would avoid adding more circuits.

 

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I think the reason they dont do the "daisy chain" thing is that they want people to have flexibility...for example, you may have three LTC3777s with wanted 120 degree degree clocks...or two, with 180degree clocks, etc etc....the Analog.com make these type of phase shifted oscillators so i guess they sell them aswell....i think its the Picoblox family or something.

They also make wee little boost converters so you can have some bias supply for your oscillator.

Also, AYK, there can be noise issues, due to grounding issues between the chips, with daisy chaining...but with other way, you can do sending of isolated clock etc etc
 
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Okay, now it's clear how to proceed; but I'm wondering what are the issues with not doing this (I mean just letting each controller run its oscillator asynchronously) since I'm not comfortable adding more components (even few) onto an already overpopulated PCB. BTW, this board will work remotely, so there is no problem in case of audible noise due to the beating of both switching frequencies.
 

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..if you interleave switch them, then your input and output filters can be much smaller...since the "effective " switching frequency will be double each stage's f(sw).
 

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andre_luis said:
This is a pitfull overlook from the manufacturer, as the power supply for the entire circuit is taken precisely from this SMPS, so an extra power supply would be needed to power this oscillator. Thanks for the insight.
Click to expand...
In my experience it's rare for a PWM controller from any vendor to provide an output clock, unless it's meant to be one of several controllers in an interleaved multiphase scheme (in which case the clocks can have a configurable phase shift).
This is very dependent on context, but you've certainly identified one of the main hazards of asynchronous switching circuits (intermodulation or "beating"). In general, behavior will be more consistent when clocks are synchronized.
 

    andre_luis

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Yes, though PFC stages are rarely if ever sync'd to their downstream SMPS ....never causes problematic issues, even if f(sw) the same.
 

    andre_luis

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