[PIC] CLOCK Settings in PIC18F4331

[vijaya_narayana]

Dear All
i am currently doing project in PIC18F4331 it is just to read 3 Inputs in RE0 to RE2 and to send corresponding outputs to PORTB if i am running in debug mode through PIC KIT 3 i am able read and send data but if i am programming the device i am unable to read the output data. it seems i have made mistake in configuring oscillator here with i am attaching the code for the same kindly let me know what mistake i have done.

// CONFIG1H
#pragma config OSC = HS     //  // Oscillator Selection bits (HS oscillator)
#pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
#pragma config IESO = OFF       // Internal External Oscillator Switchover bit (Internal External Switchover mode disabled)

 

[Aussie Susan]

If what you say is true (that it is a clock problem) then try programming a simple 'flash a LED' program and make sure that the code is running at the correct speed.
However the fact that your code (which you don't show us) runs in debug mode and not release mode makes me thing that you have fallen into a 'trap for young players' with regard to debugging PIC code.
The debug kernel that is incorporated into your code when you build in debug mode automatically sets all analog ports to digital mode. Therefore this can make your GPIO inputs work in debug mode and not in release mode UNLESS you always set the analog/digital mode correctly yourself. (You really should be doing this always in all of your programs.)
RE0 to RE2 have analog functions and so are almost certainly not reading your inputs correctly if this really is the problem. Unfortunately your problem description just says 'cannot read the output data' which really tells us nothing at all. You need to describe what development environment you use, what works, what doesn't and what does it do plus what you expected it to do. Showing the code (even a short but complete application) and all config options that exhibits the problem also really helps a lot. (I would have seen if this is the possible cause of your problems immediately.)
By the way, if the problem really is the oscillator then moving between debug ands release modes typically does not change behaviour - the same oscillator settings are used for both. (Only the programming function does not require the oscillator as the PicKit3 provides everything via the PGC/PGD lines.)
Susan

 

[vijaya_narayana]

// PIC18F4431 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1H
#pragma config OSC = HS          // Oscillator Selection bits (HS oscillator)
#pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
#pragma config IESO = ON        // Internal External Oscillator Switchover bit (Internal External Switchover mode enabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = ON       // Brown-out Reset Enable bits (Brown-out Reset enabled)
// BORV = No Setting

// CONFIG2H
#pragma config WDTEN = ON       // Watchdog Timer Enable bit (WDT enabled)
#pragma config WDPS = 32768     // Watchdog Timer Postscale Select bits (1:32768)
#pragma config WINEN = OFF      // Watchdog Timer Window Enable bit (WDT window disabled)

// CONFIG3L
#pragma config PWMPIN = OFF     // PWM output pins Reset state control (PWM outputs disabled upon Reset (default))
#pragma config LPOL = HIGH      // Low-Side Transistors Polarity (PWM0, 2, 4 and 6 are active-high)
#pragma config HPOL = HIGH      // High-Side Transistors Polarity (PWM1, 3, 5 and 7 are active-high)
#pragma config T1OSCMX = ON     // Timer1 Oscillator MUX (Low-power Timer1 operation when microcontroller is in Sleep mode)

// CONFIG3H
#pragma config FLTAMX = RC1     // FLTA MUX bit (FLTA input is multiplexed with RC1)
#pragma config SSPMX = RC7      // SSP I/O MUX bit (SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7.)
#pragma config PWM4MX = RB5     // PWM4 MUX bit (PWM4 output is multiplexed with RB5)
#pragma config EXCLKMX = RC3    // TMR0/T5CKI External clock MUX bit (TMR0/T5CKI external clock input is multiplexed with RC3)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (Enabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON         // Low-Voltage ICSP Enable bit (Low-voltage ICSP enabled)

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000200-000FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (001000-001FFF) not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (002000-002FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (003000-003FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot Block (000000-0001FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000200-000FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (001000-001FFF) not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (002000-002FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (003000-003FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0001FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000200-000FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (001000-001FFF) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (002000-002FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (003000-003FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0001FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

//#include <xc.h>

int hsense;
#include <xc.h>
main()
{
    OSCTUNE = 0xff;
    OSCCON = 0x72;
    ANSEL0 = 0x00;
    ANSEL1 =0x00;
    TRISE = 0xff;
    TRISB = 0x00;
    while(1)
    {
       hsense=PORTE;
       if(hsense==0x02)LATB = 0x2b;
       if(hsense==0x06)LATB = 0x2e;
       if(hsense==0x04)LATB = 0x1e;
       if(hsense==0x05)LATB = 0x1d;
       if(hsense==0x01)LATB = 0x35;
       if(hsense==0x03)LATB = 0x33;
       //if(hsense==0x00)LATB = 0x2b;
    
    }}

my entier code

 

[Aussie Susan]

My bet is that you are reading the entire port E - all 8 bits. Port E also has the PGC/PGD and other functions on the pins that you are NOT using.
In DEBUG mode some of these pins will be used for the PicKit3 ( or whatever) and so will be taken over by the debug kernel. That means the 'port' operation will always read a '0'.
However in 'release' mode those pins will be floating and I suspect that at least 1 is floating high.
Therefore when you compare the whole 8 bits to (say) 0x02, the upper bits will make the comparison false.
Therefore change to:

hsense = PORTE & 0x07;

That will force any floating inputs to be ignored when assigning to 'hsense'.
An alternative is to not make all of PORTE pis inputs. Reading for a PORT, even when a pin. is set to 'output', will read whatever is on the line that should be whatever the LAT is defining.
Susan

 

[vijaya_narayana]

is that you are reading the entire port E - all 8

--- Updated Jan 3, 2022 ---

i tried the above but still it is not working i think i will check the hardware now to see if the Crystal is working properly ..

i tried internal oscillator also still not working after programming

 

[KlausST]

Hi,

What about a

Loop
(
Invert pin
Delay
)

Test?

 

[vijaya_narayana]

tried the test during debugger it is working i am able to stop and start the process but i program the same with internal RC oscillator / external 16Mhz Crystal also not working i guess i must start looking at the internal osc mode first and then switch to external oscillaotor i changed the code to internal also as below

// CONFIG1H
#pragma config OSC = IRCIO      // Oscillator Selection bits (Internal oscillator block, port function on RA6 and port function on RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal External Oscillator Switchover bit (Internal External Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled)
// BORV = No Setting

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDPS = 32768     // Watchdog Timer Postscale Select bits (1:32768)
#pragma config WINEN = OFF      // Watchdog Timer Window Enable bit (WDT window disabled)

// CONFIG3L
#pragma config PWMPIN = OFF     // PWM output pins Reset state control (PWM outputs disabled upon Reset (default))
#pragma config LPOL = HIGH      // Low-Side Transistors Polarity (PWM0, 2, 4 and 6 are active-high)
#pragma config HPOL = HIGH      // High-Side Transistors Polarity (PWM1, 3, 5 and 7 are active-high)
#pragma config T1OSCMX = ON     // Timer1 Oscillator MUX (Low-power Timer1 operation when microcontroller is in Sleep mode)

// CONFIG3H
#pragma config FLTAMX = RC1     // FLTA MUX bit (FLTA input is multiplexed with RC1)
#pragma config SSPMX = RC7      // SSP I/O MUX bit (SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7.)
#pragma config PWM4MX = RB5     // PWM4 MUX bit (PWM4 output is multiplexed with RB5)
#pragma config EXCLKMX = RC3    // TMR0/T5CKI External clock MUX bit (TMR0/T5CKI external clock input is multiplexed with RC3)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (Enabled)

// CONFIG4L
#pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = ON         // Low-Voltage ICSP Enable bit (Low-voltage ICSP enabled)

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000200-000FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (001000-001FFF) not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (002000-002FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (003000-003FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot Block (000000-0001FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000200-000FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (001000-001FFF) not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (002000-002FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (003000-003FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0001FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000200-000FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (001000-001FFF) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (002000-002FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (003000-003FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0001FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

int hsense;
#define _XTAL_FREQ 4000000
#include <xc.h>
main()
{
   OSCTUNE = 0xff;
   OSCCON = 0x72;
    ANSEL0 = 0x00;
    ANSEL1 =0x00;
    TRISE = 0xff;
    TRISB = 0x00;
    while(1)
    {
        LATB = 0xFF;
         __delay_ms(1000);
         LATB = 0x00;
          __delay_ms(1000);
 
    }}

--- Updated Jan 3, 2022 ---

Problem solved i changed the LVP settings from ON to OFF the internal Oscillator Started to function and code is running independently

--- Updated Jan 3, 2022 ---

thank you all for the reply