Clock running, NCVer| log problem, oneshot from

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jelydonut

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this is the problem im having..

i have a clock running and at the same simulation time as the rising edge i deposit a 1 to say "signal". Then i try to create a oneshot from it.. so..

always@(posedge clk)
signal_dly <= signal;

assign signal_os = signal & ~signal_dly;

what is happening though is that because im depositing the 1 on the posedge both signal and signal_dly get assigned the 1 at the same time.. hense no oneshot is produced.. i know m0dels|m doesn't do this..

is there a setting or something i need to change or do i just kick my system across the room and hope that works?

jelydonut
 

Re: NCVer|log problem.

hi,jelydonut

I think the sturcture of DFF:
always@(posedge clk)
signal_dly <= signal;

is as same as the
assign signal_dly = signal;

It is a remarkable point in most Coding Style.

You can change the DFF to:
always @ (posedge clk or possedge rst)
if (rst)
signal_dly <= Default Values;
else
signal_dly <= signal;

assign signal_os = signal & ~signal_dly;

Then do your simulation.

Good luck!
 

NCVer|log problem.

Is

always@(posedge clk)
signal_dly <= signal;

really the as same as the
assign signal_dly = signal;

??????????????????
 

Re: NCVer|log problem.

cnspy said:
Is

always@(posedge clk)
signal_dly <= signal;

really the as same as the
assign signal_dly = signal;

??????????????????
Click to expand...

I have simulated this block in NC-Verilog. The waveforms were same. And I have refenced some Coding Styles, found this is same.

I don't know the arithmetic of different logics in the simulation tools. May you find the reason in this view?

good luck!
 

NCVer|log problem.

I don't think so.

before clk.rising, the signal value changes.

use "asssign" the signal_dly will change it's value.
But in always block with clk, the signal_dly will not
change.
 

Re: NCVer|log problem.

cnspy said:
I don't think so.
before clk.rising, the signal value changes.
use "asssign" the signal_dly will change it's value.
But in always block with clk, the signal_dly will not
change.
Click to expand...

hi, cnspy

At first, I also can't believe this. Then I write the block and simulate.

So if you have some time, you can do it in your simulator, and compare different tools.

Please tell us your result!

Good luck!
 

Re: NCVer|log problem.

Hi,jelydonut,
You are right this is a oneshot circuit.The oneshot pulse is generateing in the RISING EDGE of 'signal' . I simulated it and source code is attached.
I simulated it in Nc-verilog, so some changes may be made in modelsim.

cac

module oneshot;
reg signal_dly,signal,clk;
parameter delay=1;

initial
begin
#5;
clk=0;
forever
clk= #10 ~clk;
end

initial
begin
#7;
signal=0;
forever
signal= # 20 ~signal;
end

always@(posedge clk)
signal_dly <= # delay signal;


assign # delay signal_os = signal & ~signal_dly;

initial
begin
$shm_open ("waves.shm");
$shm_probe ("AS");
end

endmodule
 

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