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The clock gives a common information about timing.
Like the clock on the wall of a school. With the use of the clock and a schedule everyone knows which things to do at which time.
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Your question is too general.
Please ask a more elaborated, more detailed question.
I mean: "clock" can be used in very different ways. It can be used to build a digital watch. It can be used to provide a carrier frequency for RF. It can be used as metronome in music.
The clock gives a common information about timing.
Like the clock on the wall of a school. With the use of the clock and a schedule everyone knows which things to do at which time.
***
Your question is too general.
Please ask a more elaborated, more detailed question.
I mean: "clock" can be used in very different ways. It can be used to build a digital watch. It can be used to provide a carrier frequency for RF. It can be used as metronome in music.
I guess you almost answered your question yourself.
The clock is the timing control for the sequencer.
A sequence is "a particular order in which related things follow each other". (accroding internet search)
Back to the school class:
The sequence on monday may be: physics, mathematics, sports, ...
But for the pupils and the teachers to know when each lesson starts .. the schedule needs a timing information.
(like: maths from 9:00 to 10:00)
And both pupils and teachers need a common clock to refer to.
The clock is the "timing source".
Electronics example.
Build a blinker for a car. 0.5s ON, 0.5s OFF (ON and OFF are the sequence, 0.5s is the timing information)
* Now in simplest case you may have a 2Hz clock. --> at one rising edge: ON, at the next rising edge: OFF
* or you have a 1MHz clock: 500.000 clock ticks ON, 500.000 clock ticks OFF
A clock signal is often used to make things happen. Inside a computer is its central processing unit. By feeding it one pulse it executes a step in a program. Feed it another pulse and it goes on to the next step. Etc.
1) RTL level: For latch registers to sample signals from launch registers only at clock edge. So ignoring variable delay during a clock period.
2) design level: to control sequence of events and processing.
However clock forces a bottleneck for logic and an asynchronous approach has been considered but is hard and I am not sure if it is being successful in fpga market. see link below about Achronix products.
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