Clock output from FPGA

kirill · Mar 17, 2011

Hello!
Xilinx Spartan 6
Is there any method to output clock from FPGA, except using ODDR2 component?
I need to output to external circuit divided or multiplied clock signal from pll. When i tried to assign output from pll to output of vhdl module, ISE generate error about unroutable situation, and suggests to use oddr2 or constraint NET "XXX" CLOCK_DEDICATED_ROUTE = FALSE(may cause signal skew). FPGA has GCLK pins, that directly attach to global clock net through bufgs, when i tried to attached output of pll to gclk , the same error happened. So, to output clock i have to use only ODDR2, or write constrain, no other methods?

mrflibble · Mar 17, 2011

Since as far as I know for a spartan-6 there are no dedicated clock outputs, you might indeed want to use an ODDR2 as clock output. Feed it with clk and ~clk for C1 and C2 respectively, with a 0 and 1 respectively for the two data inputs of the ODDR2 primitive.

kirill · Mar 17, 2011

thank you for reply!
Yes, I 've already done with a help of oddr2. But it is interesting, if we have dedicated pads, that connected to global clock net, why we can use them as inputs, and cant use them as outputs?
"Since as far as I know for a spartan-6 there are no dedicated clock outputs" do other FPGAs have dedicated outputs?

gl.a · Aug 29, 2012

Hello! Thak you for this information, i have the same problem. I am still having it because it allows to implement but there is no clock on Q aka the output of the ODDR2. I have a warning: Xst:2016 - Found a loop when searching source clock on port 'i2s_mclk_in_neg:i2s_mclk_in_neg'

My instation:

Code:

ODDR2_inst : ODDR2
generic map
(
	DDR_ALIGNMENT => "NONE",
	INIT => '0',
	SRTYPE => "SYNC"
)
port map
(
	Q => i2s_mclk_final, 
	C0 => i2s_mclk_in,
	C1 => i2s_mclk_in_neg, 
	D0 => '0', 
	D1 => '1'
);

i2s_mclk_in_neg <= not(i2s_mclk_in); (this is because i heard that its problematic if i negate it on the fly)

i2s_mclk_in is the output of the DCM.

I have checked with the simulator and in the real pin either, but there is constant 0 there. What could be the problem?

Best regards,

kirill · Aug 29, 2012

https://www.edaboard.com/threads/204985/

gl.a · Aug 29, 2012

I have read it, but i'm still confused. (i lurked every similar topic, and i read the official xilinx primitive usage guide) Could you explain it to me? Or maybe it's better if i sleep on it. I'm guessing i do a silly mistake.

mrflibble · Aug 29, 2012

Quick tip: that "if I negate it on the fly I shall meet my dooooOOOoom" is for older fpga's. On the spartan-6 you have local clock inversion, so for a ODDR2 like this you can do:

Code:

port map
(
	Q => i2s_mclk_final, 
	C0 => i2s_mclk_in,
	C1 => not(i2s_mclk_in), 
	D0 => '0', 
	D1 => '1'
);

If you have any doubts it doesn't do what it should, synthesize it and check the result in fpga editor. Then you'll see that the MUX for local clock inversion gets used. And I suspect this also will magically solve your warning for you. Also, check the clocking resources bit for spartan-6 for details on the local clock inversion feature.

gl.a · Aug 29, 2012

Thank you for your answer but, i tried both, as you write too and if i negate there, i got a different warning and it's still not working:
Actual for formal port c1 is neither a static name nor a globally static expression:grin:

mrflibble · Aug 29, 2012

Well, I use the exact same ODDR2 construct to generate a clock output (admittedly in verilog) and that works just fine.

I was of course assuming that i2s_mclk_in is not some random stuff, but a real actual valid clock on a global clock net.

Maybe the negate construct with a "not" results in it not valid. VHDL really isn't my strong suit. Well, you can always RTFM at the section I suggested earlier and see if xilinx has a VHDL code template for precisely this case.

BlackHelicopter · Aug 30, 2012

The "loop" warning mentioned above is interesting because I remember getting the exact same warning when I followed the "Clock Forwarding" section in one of the Spartan application notes, using ODDR2 and OBUF as suggested (using a Spartan 6 as well). I never did get the warning resolved, however I did achieve a clock on one of the pins, I really thought it might be a bug in their tool but was never really sure. If someone knows the answer to this I'm all ears.

mrflibble · Aug 30, 2012

As BlackHelicopter alludes to, it probably has to do with the buffer on i2s_mclk_in. If you generate that from a DCM module generated from core generator, then you should pay some attention to the output buffer on that module.

Another bit of useful documentation to read is on IODELAY2 for the spartan-6. And yes yes, that has nothing to do per se with ODDR2, but but but ... it does have everything to do with amusing restrictions and gotchas regarding precisely this sort of clocking.

gl.a · Aug 31, 2012

I tried to instantiate and set up the DCM manually:

Code:

DCM_CLKGEN_inst : DCM_CLKGEN
generic map
(
	CLKFXDV_DIVIDE => 2, -- CLKFXDV divide value (2, 4, 8, 16, 32)
	CLKFX_DIVIDE => 1, -- Divide value - D - (1-256)
	CLKFX_MD_MAX => 0.0, -- Specify maximum M/D ratio for timing anlysis
	CLKFX_MULTIPLY => 4, -- Multiply value - M - (2-256)
	CLKIN_PERIOD => 0.0, -- Input clock period specified in nS
	SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
	-- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
	STARTUP_WAIT => FALSE -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
)
port map
(
	CLKFX => i2s_mclk, -- 1-bit output: Generated clock output
	CLKFX180 => open, -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
	CLKFXDV => open, -- 1-bit output: Divided clock output
	LOCKED => open, -- 1-bit output: Locked output
	PROGDONE => open, -- 1-bit output: Active high output to indicate the successful re-programming
	STATUS => open, -- 2-bit output: DCM_CLKGEN status
	CLKIN => sys_clk, -- 1-bit input: Input clock
	FREEZEDCM => open, -- 1-bit input: Prevents frequency adjustments to input clock
	PROGCLK => sys_clk, -- 1-bit input: Clock input for M/D reconfiguration
	PROGDATA => open, -- 1-bit input: Serial data input for M/D reconfiguration
	PROGEN => open, -- 1-bit input: Active high program enable
	RST => clk_gen_enable -- 1-bit input: Reset input pin
);

No error, no warning, still no clock.
In the simulator i didn't forget to set to '1' the RST aka clk_gen_enable.

(i didn't set the divider and multiplier but that's doesn't matter now)

PS: there's a lot of error while MAP-ing

mrflibble · Aug 31, 2012

Did you read the suggested documentation yet? Just asking...

And I ask because if you get them thar mapping errors it's quite likely you did not read the suggested docs. I know, because I neglected to fully read the docs as well during my first attempt, and I got plenty of mapping errors. And indeed, synthesizes just fine. That's nice, but you need it to map as well... You get the mapping errors because you violate the rules of what kind of clocking output you can plug into your favorite ODDR2 resource. Or DCM. Or PLL. Read docs. Docs are your friend. And at least the clocking resources docs for spartan-6 from xilinx are quite readible, so no excuse to not read it. ;-)

permute · Sep 3, 2012

mrflibble said:
Well, I use the exact same ODDR2 construct to generate a clock output (admittedly in verilog) and that works just fine..

This is because verilog will evaluate expressions connected to ports while VHDL will only do this for type conversions (if at all). some compilers will be more lax about this for VHDL, but many aren't. the issue is that "not(clk)" isn't a signal and VHDL won't evaluate the not(). the solution is to create a signal called clk_n, and assign it to clk_n <= not clk;

mrflibble · Sep 3, 2012

Thanks permute, good to know. Looks like my new poster auto classification filter owes gl.a 80% of an apology. I was thinking 80% chance he just stuffed it up elsewhere with the clock source, and 20% chance it's something vhdl-ish. Of course on the off chance it was something like this I did include this bit:

mrflibble said:
Well, you can always RTFM at the section I suggested earlier and see if xilinx has a VHDL code template for precisely this case.

On that subject, UG381 chapter 2 has some useful info.

Clock output from FPGA

kirill

Member level 5

mrflibble

Advanced Member level 5

kirill

Member level 5

gl.a

Newbie level 4

kirill

Member level 5

gl.a

Newbie level 4

mrflibble

Advanced Member level 5

gl.a

Newbie level 4

mrflibble

Advanced Member level 5

BlackHelicopter

Full Member level 2

mrflibble

Advanced Member level 5

gl.a

Newbie level 4

mrflibble

Advanced Member level 5

permute

Advanced Member level 3

mrflibble

mrflibble

Advanced Member level 5

Similar threads

Clock output from FPGA

Member level 5

Advanced Member level 5

Member level 5

Newbie level 4

Member level 5

Newbie level 4

Advanced Member level 5

Newbie level 4

Advanced Member level 5

Full Member level 2

Advanced Member level 5

Newbie level 4

Advanced Member level 5

Advanced Member level 3

Advanced Member level 5

Similar threads

Privacy & Transparency

Privacy & Transparency