praveenkrs
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Hi,
I'm synthesizing a digital core using Synopsys DC, with a given clock, and I will later use this clock to drive the next blocks. Since the network will introduce a clock latency, I wanted a dedicated clock out port which outputs this delayed clock.
How do I go about it?
I tried to just to put a buffer and output the buffer output, but I'm guessing that's not a right way, as even that is not the right clock.
Any suggestions?
I'm synthesizing a digital core using Synopsys DC, with a given clock, and I will later use this clock to drive the next blocks. Since the network will introduce a clock latency, I wanted a dedicated clock out port which outputs this delayed clock.
How do I go about it?
I tried to just to put a buffer and output the buffer output, but I'm guessing that's not a right way, as even that is not the right clock.
Any suggestions?