Can a clock mux remove glitches if we need to connect the inputs of the clock mux with signals which are not clocks but these signals can produce glitches?
Clock mux in general makes the output glitch free. When both the clocks are low and the select signal is toggled; it switches output. If it works for clock; it should work for other signals as well.
The glitch-free feature depends on synchronisation of the mux control signal to the clock input. In a synchronous logic design, other signals than clocks are sampled at clock edges and don't need to be glitch-free outside the setup- and hold window.
In other words, it's almost unclear what you want to achieve. What do you exactly mean with " these signals can produce glitches"?
The glitch-free feature depends on synchronisation of the mux control signal to the clock input. In a synchronous logic design, other signals than clocks are sampled at clock edges and don't need to be glitch-free outside the setup- and hold window.
In other words, it's almost unclear what you want to achieve. What do you exactly mean with " these signals can produce glitches"?
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Not quite right. Clock muxes allow glitch free clock switching. If the input clock itself has glitches, you are lost.
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Referring to the thread title "eliminate glitches in input signals".
A clock mux does never eliminate gliches in input signal, neither for clocks nor other signals.
There were clock muxes found in design with input signals which are not clocks. The signal which are input to these clock muxes can produce glitches. It is not understood the reason for presence of clock muxes instead of normal muxes in the design. Hence this thread is started. Why normal muxes are not used here and clock muxes are used?
Is clock mux found in library is same as glitch free clock mux? What are the differences between a clock mux found in library and a glitch free clock mux if clock mux found in library is not same as glitch free clock mux?
The mux control would cause the clkm to be produced as the clock immediately switches from clk0 to clk1. This results in a glitch.
The clock muxes I've seen will not switch the clock until it sees the edges of the clock and shuts off the mux output until an edge is seen on the clock being switched to resulting is something similar to the clkg output. In this example the clock being switched from (clk0) isn't switched away from until the clock pulse is 0 and the output doesn't immediately output clk1 until the next clock edge.
This is a simplified version of what a number of clock muxes I've seen are meant to do, they don't filter glitches they just avoid producing glitches on the clock switch over.
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Whoever used a clock mux to "filter" glitches doesn't know what they were doing.