clock multiplication by 2

[verilog_coder]

clock multiplier verilog

How to implement clock multiplication in verilog???

 

[echo47]

clock multiplier in verilog

For simulation or for synthesis? Is the clock rate known or unknown?

 

[aravind]

verilog clock multiplier

for synthesis he is asking .
me too wanna know how mutiplication clock can apply.
like divide by 2 clk in DC /RTL compiler commands

 

[anjali]

clock multiplecation by 2

pass direct clock and delayed clock to an XOR gate. we can get multiply by 2 clk.

 

[aravind]

clock multiplier + verilog + code

yes what ur telling it is correct when the timing arc of a>z or b>z must t/2 delay.
otherwise it wont work

 

[verilog_coder]

clock multiplication logic rtl

Thanks for the help. i wan to know how to make the clock of 50% duty cycle. Ofcource in a way that can be implemented in verilog (Synthesizable).

 

[zhustudio]

multiply by 2+xor

You can think in circuits level. If only logic applied, you can not give 2X clock in gate level. So you can not use verilog code to give 2X clock out.
Delay methods is a simple way but un-robust way to give 2X clock. If you must please use simple PLL or DLL circuits.

 

[verilog_coder]

clock multiplication verilog

To be implemented in verilog i mean that the circuit should not include the custom ics.

 

[aravind]

clock multiply with two verilog

what zhustudio think is correct in some point.
but discussion here is pure logic synthesis area.
so no analog/custom ic.
how we can multiply clock freq ?
i think only if xor can able to do . but i have lot problem.
any one experience like that problem?

 

[anjali]

clock multipliers in verilog

in general, we will not do clock multiplication at logic level. generally its not preffered. its better to use PLLs for that.

 

[verilog_coder]

clock multiplier verilog code

So i assume it is impossible to implement clock multiplication circuit in verilog RTL

 

[uckingcu]

multiply clock gate

hi..i think you have to dleay the clock by clock period/4 ..so how would you do that?

 

[jackson_peng]

verilog multiply clock input

hehe, in digitial word, we use edge to trigger another edge.

for clock multiplication, how can we create a clock edge from nothing?

 

[leonlin520]

verilog clock delay

You can think in circuits level. If only logic applied, you can not give 2X clock in gate level. So you can not use verilog code to give 2X clock out.
Delay methods is a simple way but un-robust way to give 2X clock. If you must please use simple PLL or DLL circuits.

 

[funzero]

multiply clock by 2 verilog

module clkmultby2(clock_in , clock_out);
input clock_in;
output clock_out;
wire a,b,c;
inv (b,a);
xor (c,a,clock_in);
dff u_dff( .clock( c ) , . d(b), .q( clock_out) );
buf (a , clock_out);
endmodule

it is not full 50% multiple clock .

 

[AlexWan]

verilog clock divider

Hi verilog_coder,
You can find a paper named "Clock Dividers Made Easy" in SNUG. This paper will tell you how to divide clock, and duty cycle is 50% in Verilog.

Good Luck

 

[gliss]

multiplication of clock by 2

AlexWan, verilog_coder wants to multiply the clock, not divide it.
You should use a DLL to multiply it. Or use vendor specific technology. Either way, hand coding a clock multiplier in HDL is not a good idea.

 

[visualart]

clock multiplier+verilog

a simple methdology ------ using hte edge posedge and the negedge.

 

[farmerwang]

generating a 2x clock xor

You have to use a DLL to delay the clock by 1/4 cycle and XOR with origianl clock.

 

[gliss]

how to multiply the clock using verilog

a simple methdology ------ using hte edge posedge and the negedge.

If your design lets you be sensitive to the negative and positive edges, then maybe. It also depends if the duty cycle is acceptable for you to use.