Clock multiplication and clocking question

[whack]

Need some practical advice.

My custom circuit, which will be based around an FPGA or CPLD, uses 14, 28 and 56MHz clocking. The device I'm interfacing my circuit to supplies two clock signals, a 7MHz clock and a quadrature clock, also 7MHz but 90 degrees out of phase. Obviously I can run those two clock signals into a XOR gate and get a 14MHz clock, but what solution would also give me 28 and 56MHz clock? I need the 14, 28 and 56MHz clocks to have their clock edges aligned.

I was thinking perhaps to make the 56MHz clock signal and just provide that to the FPGA or CPLD as the clock input, and then divide it into 14 and 28 using counters internally.

But what's the best way to make the 56MHz clock signal, using the two 7MHz clock inputs I have (one being quadrature)? I'd like this clock signal to be low jitter, and need valid solution(s) for both FPGAs and CPLDs.

Advice is appreciated.

 

[barry]

You can use the internal PLL or DLL in an FPGA (it will add some jitter) to generate your clocks. I don't like the XOR idea because you probably won't get a 50% duty cycle. If you use a counter, your clock edges won't be aligned due to propagation delay.

 

[whack]

You can use the internal PLL or DLL in an FPGA (it will add some jitter) to generate your clocks.

I've read about jitter from those. My only experience is with DLL (Spartan 3E), and its more jittery than desired. Any other options?

What about something for a CPLD?

If I do use a PLL, would I just need one of the 7MHz clock inputs?

I don't like the XOR idea because you probably won't get a 50% duty cycle.

True about the duty cycles. If using just rising or just falling edges the duty cycle might not play a role, but I hadn't checked. Probably not a good practice either way.

If you use a counter, your clock edges won't be aligned due to propagation delay.

I agree, but it should be close enough for my purposes. I will avoid counters if possible nevertheless.

 

[FvM]

FPGAs have a PLL that can generate the intended multiple clocks. There are a several reasons why logic generated clocks (frequency dividers etc.) are avoided. You didn't yet tell specific requirements that might substantiate a different decision.

If you don't have PLLs available, e.g. in a CPLD or discrete logic based design, a high frequency input clock with dividers might be solution. Consider that a divided clock won't be edge aligned with the master clock. Furthermore, it's not sufficient for a timing closure of a multi-clock domain design to have the clocks edge-aligned. Detailed timing analysis is required.

 

[whack]

FPGAs have a PLL that can generate the intended multiple clocks. There are a several reasons why logic generated clocks (frequency dividers etc.) are avoided. You didn't yet tell specific requirements that might substantiate a different decision.

I originally wanted to use a CPLD, and that won't have had a PLL, mostly for PCB simplification (no PROM). If I understood correctly PLLs can have a long startup time, in addition to the generally longer startup time an FPGA has compared to CPLD.

If I were working with a Xilinx FPGA, how many PLL instances would I need to get the three clocks I need (14, 28 and 56MHz)? This would affect my FPGA selection, right?

I was looking through chip supplier catalog and had a hard time finding a Xilinx FPGA for 3.3V logic that also has a PLL. I did find Lattice parts though. Any experience with those?

If you don't have PLLs available, e.g. in a CPLD or discrete logic based design, a high frequency input clock with dividers might be solution. Consider that a divided clock won't be edge aligned with the master clock. Furthermore, it's not sufficient for a timing closure of a multi-clock domain design to have the clocks edge-aligned. Detailed timing analysis is required.

For this scenario can you propose a way to generate that 56MHz master clock from the 7MHz clock input I have available?

It seems that this discussion is going in the direction of strictly FPGAs and CPLDs, could you do me a favor and move this thread to the appropriate FPGA/CPLD section?
Like here perhaps:
https://www.edaboard.com/forums/30/

Thanks!

 

[FvM]

If minimum part count is an objective, I would e.g. use a small Altera MAX10, a FPGA with built-in configuration flash, available in a 3-3.3V single supply version. Even the smallest (2k logic elements) device has 2 PLLs with 5 outputs each, one oPLL can generate all required clocks for your application.

For Xilinx or Lattice devices with similar specs, others should make suggestions.

x8 clock multiplication needs a PLL. If you don't have it, the input clock must be 56 MHz.

 

[whack]

If minimum part count is an objective, I would e.g. use a small Altera MAX10, a FPGA with built-in configuration flash, available in a 3-3.3V single supply version. Even the smallest (2k logic elements) device has 2 PLLs with 5 outputs each, one oPLL can generate all required clocks for your application.

How are the tools for Altera? What's the learning curve like going from Xilinx ISE?

x8 clock multiplication needs a PLL. If you don't have it, the input clock must be 56 MHz.

The interface I will connect my custom module to gives just the two 7MHz clocks, quadrature. There is the master clock a 14MHz crystal oscillator elsewhere on the board, but I'd have to tap that and run a wire, about 3-4 inches. That would reduce multiplication down to 4x, with this do I have more options?

 

[CataM]

For this scenario can you propose a way to generate that 56MHz master clock from the 7MHz clock input I have available?

Why don't you go to the Soft IP given in the ISE Xilinx tool and use the DCM to make that ?

 

[barry]

I'm not sure, but I think 7mhz might be too low a frequency for the DCM.

 

[CataM]

I'm not sure, but I think 7mhz might be too low a frequency for the DCM.

For the DFS is good enough even for the old Spartan 3 family.


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Read DCM's datasheet for Xilinx FPGA families and see what fits best to your needs.