I've never used a sinusoidal clock - it would be difficult to guarantee timing in any CMOS process (due to Vt variations) with a sinusoid. Ofcourse when you go to really high frequencies the clock may tend-toward a sinusoid - but it's not desirable.
There very possibly is an application where a sinusoid is prefferable as a clock (It would contribute less noise ot a system), but I can't think of one of-hand.
when it goes to high frequency, like ~100M, the clock signla will mostly look like sinusoidal no matter how hard you try to make a fast rising and falling edge, there will always be parasitics to degrade the edges.
The clocks will not intentionally be sinusoidal. But a the edges of any squarewave clock will have charge and discharge chareceristics. At very high frequencies, the pulses are so narrow that an increasing percentage of the clock is the charge-discharge curves. So they're not really sinusoidal, but they're not square either.
I'm not sure what your question about PLL's is.
There are several types of PLL, ones used for multiplying clocks (these come in 2 flavours), and ones used in TV sets and the likes which lock to sine waves (the sinewaves in this case are not clocks), I'm not sure in the case of the latter that allthe internal signals will be sinusoidal.
AA,
In GHz range the signal rise & full times is large, so the clock will be not much affected if it's generated as sinusoidal & then it passes through chain of inverter to work as buffer, then it will be likely square wave.
Many PLL clock generators use LC VCO for its low phase noise performance, however its output is sinusoidal
I hope I came to the right point
best regards,
Rania