clock insertion delay

Status
Not open for further replies.
M

memdes

Newbie level 1
Newbie level 1
Joined
Jul 14, 2011
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,285
How is clk insertion delay in a liberty model of a memory used by soc designers?
 

To balance clocks between two IP's
 

Status
Not open for further replies.

Similar threads