clock init problems unwanted /8 division

[reven]

clock init problems

i am using a renesas m306n4fggp uC and i have set the following setting in order to initialize the main clock:

PRCR |= (1<<PRCR_PRC0);
cm0 &= ~(1<<CM0_CM06);
cm0 |= (1<<CM0_CM04);
cm0 &= ~(1<<CM0_CM03);
cm1 &= ~(1<<CM1_CM15);
cm0 &= ~(1<<CM0_CM05);
cm1 &= ~(1<<CM1_CM11);
cm2 &= ~(1<<CM2_CM21);
cm0 &= ~(1<<CM0_CM07);
plc0 &= ~(1<<PLC0_PLC01);
PRCR &= ~(1<<PRCR_PRC0);

the problem is that i dont want any divition and still got /8 division with these settings.

do i have to set anything else or there must be a different order so that changes take place?

 

[Gomez]

Re: clock init problems

Could you post register values after initialisation for CM0,CM1,CM2,CCLKR ?

Gomez