[SOLVED] Clock generator in verilog?

[krishanu007]

I want a synthesizable clock generator code in verilog.
please dont give me always #delay clk = ~clk
& dont tell me to search google for PLL..
give me material (picture or block diagram or explanation of code) of how its done.:grin:??

 

[kornukhin]

You can't create generator without external reference clock signal.
So you can only create digital dividers with verilog. You can alse crete ,ultipliers using xor but this requires detailed timing analyses.

// divide-by-2
////////////////////////////////////////////////
input ref_clk;
output reg clk;

always@(posedge ref_clk)
clk<=~clk;
////////////////////////////////////////////////


// multiple-by-2
////////////////////////////////////////
input ref_clk;
output clk;
wire delay_ref_clk;
buf(delay_ref_clk, ref_clk); // this delay used to create new clock pulses
xor(clk, delay_ref_clk, ref_clk);
////////////////////////////////////////

 

[hamidmoallemi]

hi
what do you mean synthesize clock generator in verilog?
on which platform do you want to synthesize your code?
if you use FPGA you must have a physical oscillator anyway
such as an external crystal oscillator or so,and you can use PLL or prescaler code in verilog to
increase or decrease of clock frequency.

"always #delay clk = ~clk"
is just for simulation in test bench!

also you can try inverter ring oscillator but i'm not sure it work or not!