Clock generator circuit (obtain a plot from other plots)

[AllenD]

Hi All,
Can I please ask some help about clock design.

In the attached picture there are 4 clock plots. For each one of the clock plot, there are 2 clocks signals(8 clocks scheme in total but they are sorts of similar). The upper one is the goal and lower one is what I have for now. Basically, I want to make every other clock high disappear.

Can you please let me know how to generate the upper clock from the lower clock?

 

[KlausST]

Hi,

All 8 signals have names, but you don't use this names, therefore I'm confused which signsl you refer to.
To ease this you may number the signal from 1 (upper) to 8 (lower).

What is your input signal?
What is your desired output signal?
Do we need to care about all the other shown signals?

It's not clear what you need.
If you need code, then show us your code first.
If you need a schematic, then show us your circuit first.
If you need equations....

***
I'm guessing that you talk about an FPGA solution using VHDL....
If so, then mind that every generated "output" signal should be a clocked signal ...clocked from one edge of the input signal.
This means that output changes state only on one edge (often rising edge) of the input clock
--> no output change on the falling input clock edge.

For sure it is possible with combinatorial logic, but you should avoid it.
Rather use an input clock with twice the frequency.

Klaus

 

[AllenD]

Thanks for your reply. My bad.
The input signal is 2,4,6,8
and the desired output signal is 1357.
I need a circuit schematic 1/2 the freq with 1/4 duty-cycle.

Thanks

 

[AllenD]

Clock generator circuit schematic


Hi All,
Can I please ask some help about clock design in the sense of circuit.

In the attached picture The upper one is the desired output signal and the lower one is the input signal. Basically, I want to make every other clock high disappear. Aka, half the clock freq with 1/4 duty cycle.

Can you please let me know what circuit can generate the upper clock from the lower clock?

 

[betwixt]

Re: Clock generator circuit schematic

Divide the lower waveform by 2 then AND it with it's original. With the exception of propagation time, that will allow the passage of the original only on every second pulse.

Brian.

 

[KlausST]

Hi,

In detail this is not possible, because the edges of the output signals are earlier than the edges of the input signal.

But as a raw solution..I'd use a toggle flip-flop (clocked by the clock input)
And use an AND gate to combine clock_input with flip-flop_output...to get about the desired waveform.

Mind that this combinatorial output is not the usual way. You need to check against possible glitches in the output signal.

Klaus

 

[AllenD]

Hi Klaus
Thanks. I tried your way and I have encountered a little bit problem. When I use the D flip-flop as the freq divide by 2 circuits and the output have some random 180-degree phase change. Like an inverter. I believe it is due to the circuit is uncertain at which place to start to divide the freq by 2. So there is 2 possible output with 180 degree phase shift. Do you know how to get tid of that?

Thanks
Allen

- - - Updated - - -

Hi Brian
Thanks. I tried your way and I have encountered a little bit problem. When I use the D flip-flop as the freq divide by 2 circuits and the output have some random 180-degree phase change. Like an inverter. I believe it is due to the circuit is uncertain at which place to start to divide the freq by 2. Since the period is doubled, there is only one rising edge when previously there were 2 rising edges. So there is 2 possible output with 180 degree phase shift. Do you know how to get tid of that?

Thanks
Allen

 

[dick_freebird]

A ring (Johnson) counter would do what you ask, I
think.

You can look at "pulse swallowing" too, if you're up
against the technology's speed limits (see this on
PLL prescalers, like a 4/5 prescaler front end where
no way will you get 6GHz through a complex inter-
stage carry logic).

Getting initialization (or better yet, "self-righting"
count behavior is a chore for you. Get your mind
right, about what indicates proper phase and then
you can implement it logically. There may be in fact
no difference between "0" and "180" as far as the
circuit's function goes, but such ambiguity does
pose a real headache for test development and
production test execution. You may need to have
a reset (POR?) just to make things consistent enough
to test repeatably, even if there is no application
purpose or benefit (and it's sure to add an increment
of slowness, by making nand2 into nand3 somewhere).

 

[KlausST]

Hi,

Thanks. I tried your way and I have encountered a little bit problem. When I use the D flip-flop as the freq divide by 2 circuits and the output have some random 180-degree phase change. Like an inverter. I believe it is due to the circuit is uncertain at which place to start to divide the freq by 2. So there is 2 possible output with 180 degree phase shift. Do you know how to get tid of that?

A clock signal is considered to be continous, it has no start and no end. There is no even edge and no odd edge....
If you want to do this, then you need an extra signal, like START, STOP, RUN, RESET or something else.
This signal needs to RESET the flip-flop...and to disable the clock or disable the output.
OUTPUT = clock_input AND NOT_flip-flop_output.

Klaus