Clock generation in DC

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3wais

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I'm using design compiler to generate a clock as following:

create_generated_clock -multiply_by 1 -duty_cycle 15 -source CLKIN_X2 [get_ports MUX5/sel]

this should create a %15 duty cycle clock and tie it to MUX5/sel but it doesn't. in my netlist MUX5/sel is connected to ground. why?
 

create_generate_clock, just indicate the signal starting from the ports MUX5/sel is a clock, related to CLKIN_X2, with a certain mutiplication factor and ratio factor, but DC will not generate for the logic to generate this logic.
I think you miss something in the design philosophy.
RTL made the logic.
DC transforms this code into netlist, only test structure like scan, scan-kompression, specific addition test point, or really specific stuff are inserted by DC or any synthesis tool, you must avoid netlist creation in DC as you did not validate it during the simulation phase.
 

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