clock gating while writing rtl

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sun_ray

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What should be written in the RTL to incorporate necessary clock gating?
 

Your question doesn't suffice what you want?

But still clock gating module are quit simple as below.

**************************************************
module clk_gate( clkin, en, test_en, clkout);
input clkin, en, test_en;
output clkout;

wire n1, n2;

assign n1= test_en | en;

latch_p inst_latch_p (.en(~clkin), .d(n1), q(n2));

assign clkout = n2 & clkin ;

endmodule

module latch_p ( q, d, en);
input d, en;
output q;
reg q;

always @ (e or d) begin
if (e)
q<=d;
end

endmodule
*************************************************************
 

You have not written how the rtl for the flipflop also whose clock need to be gated. Please write and complete that.

I was looking for some statements to be written in rtls, so that clock gating is inferred automatically while doing synthesis and when necessary.
 

Below is the process that will synthesize to a flop with positive edge triggered clock, asynchronous positive edge reset and clk gating will be inferred. The main idea is to have enable controlling whether data content of the flop changes or not.

Code: 
always @ (posedge clk, posedge rst) begin
  if(rst) begin
     reg <= 1'b0;
  end else if(enable) begin
     reg <= signal;
  end
end
 


morris_mano

Will the synthesis tool automatically be able to infer and pick up that clock gating cell for this kind of rtl which you coded? Thanks for your reply.

What do you suggest about the code by rocking_vlsi?

Regards
 

sun_ray said:
morris_mano

Will the synthesis tool automatically be able to infer and pick up that clock gating cell for this kind of rtl which you coded? Thanks for your reply.

What do you suggest about the code by rocking_vlsi?

Regards
Click to expand...

sun_ray,

rocking_vlsi has given code for clock gating cell itself. While synthesizing, you will have option to tell the tool whether to use the standard cell (clk gating cell) that may come up with the standard cell lib or you could write your own rtl like rocking_vlsi has done. Then wherever, the synthesis tool infer clock gating cell, it will insert the clock gating cell with the one you have specified.

Regards.
 

morris_mano

1. Will the synthesis tool will infer clock gating cell from the standard cell library, if we use the code of rockin_vlsi?How will the synthesis tool will infer the clock gating cell from the rtl of rocking_vlsi if the synthesis tool is not using the clock gating cell from the standard cell library for the code of rocking_vlsi?
2. Is it for your code the synthesis tool will mandatorily infer a clock gating cell from the standard cell library with a flipflop?
3. What is the command that should be provided to the synthesis tool to infer clock gating cell? Is it that if this command is provided to the synthesis tool, it will mandatorily do all clock gating from the clock gating cells of the standard cell library?

Regards
 

Some tools can identify the clock gating cells. If you are in asic design, it is better to instantiate standard clock gate cell from lib and provide its model file.
 

Sun_ray,

1. you will have to specify the tool that the clk gating module the rocking_vlsi has shown is the one you want to use
2. Most likely
3. depends on which synthesis tool you are referring to but they will be similar to 'set_clk_gating_cell -name "cgc". If you have manual instantiation of clk gating module and provide information to the tool, it is smart enough to understand it is clock gating cell and not touch it. However the tool can also insert clock gating cell on its own with standard cgc wherever it infers clock gating in RTL.

hope this helps
 

Morris_mano

After synthesis the clock gating cell will be realized in terms of logic gates. Suppose I used the code of rocking vlsi. Will the synthesis tool infer the standerd cell of clok gating cell? How will the tool infer the code of rocking vlsi if the tool does not infer the rtl with a standard cell of clock gating cell?

The reason again I asked the kind of question because I want to understand it better.

Regards
 

You need to understand the difference between actual instantiation of clock gating cell and inferred clock gating cell. Do you have options of running simple synthesis flow? Try running with a design where you have instantiated clock gating cell of rocking_vlsi module as well as using RTL as I have described earlier. After synthesis, if you do clock gating report, it will show two types of clock gating in the design. One instantiated and one inferred. Doing this will give you clearer understanding , rather than me trying to explain it. For instantiated one, you can manually instantiate standard cell clock gating cell also, or rtl level clock gating cell as shown by rocking_vlsi.
 


I cannot access synthesis now. But I work in synthesis also. Please answer the following:

1. Will the rocking_vlsi code infer to a standard clock gating cell from the standard cell library?

2. Will the rocking_vlsi code infer the clock gating cell with help of basic AND, LATCH cells from standard cell library?

Answering the above question will make the understanding netter.
 

morris_mano said:
1. No.

2. Yes.
Click to expand...

Morris_mano

Thank you for your answers. Can you please answer the followings:

1. Is it that your code will definitely infer a clock gating cell named 'cgc' from the standard cell library if you put the following command in your synthesis script?

'set_clk_gating_cell -name "cgc"

2. Is there any way or any synthesis command so that rocking_vlsi code infers a clock gating cell from the standard cell library?

Regards
 

1. please refer to low power synthesis flow user guide of your tool. There are various other switches you may need to turn on.
2. not that I am aware of
 

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