[SOLVED] Clock gating in synopsys flow

[kyonglee]

Hello all,

I have two instances in my top module. Say they are u1 and u2.
I would like to insert clock gating cells for each of u1 and u2 and raised some questions.
Could you answer my following questions?

1. I think clock gating cells can be inserted in either front-end (e.g., RTL level) or back-end (e.g., P&R). Which one is a better choice?

2. It seems that design compiler can insert clock gating cells. However, it seems that the design compiler places clock gating cells at the spots which meet some constraints, otherwise no clock gating cells will be put: it does not just place the cells at u1 and u2. How can I write a script to make the design compiler puts the cells wherever I want?

Many thanks!

- Kyong

 

[ljxpjpjljx]

which tool you use?

 

[dianin]

Clock-gating can be inserted automatically at systhesis level. If you want to insert it using design compiler, make sure the register banks in your design are load enable. Also the register banks should have the resonable size . The default value for -min_bitwidth swicth (for command set_clock_gating_style ) is 3, generally if the size is below 3 , it won't be useful for power saving.

 

[lostinxlation]

I don't get what you are trying to do. Do you mean you want to add clock gating cells only in u1 and u2, or are you trying to specify the exact points in logic to place the clock gating cells. THe purpose of clock gating is saving power and adding them wherever you can serves for that purpose.

Whether doing it with RTL or synthesis tool depends on the nature of the clock gating. The tool can do it for some obvious cases such as shutting down the flops when no write is performed or blocks running exclusively, but the tool may not be able to do it in some cases that involve the understanding of the application behaviors.

 

[kyonglee]

Hi ljxpjpjljx,
I am using design compiler for synthesis and astro for p&r.

Hi dianin,
Thank you for your answer! By the way, can I ask what you mean by 'load enable'?

Hi lostinxlation,
Thank you for your answer!
I want to specify the exact location for clock gating cells placement.
I actually want to force the tool to place clock gating cells at the point I want.
The following simple diagram shows what I want to do.

Clk pin --- clock gating cell 1 --- U1
Clk pin --- clock gating cell 2 --- U2

So the clock gating cell 1 controls the clock to U1 and the clock gating cell 2 controls U2.

Thank you!

 

[dianin]

Hi dianin,
Thank you for your answer! By the way, can I ask what you mean by 'load enable'?

!

load enable registers are the registers with it's output is feedback to it's input through the multiplexer , controlled by an enable signal.

If your design U1 and U2 are the load-enable register with proper bank-size, DC is able to insert clock-gating cells. But if you want to insert in layout stage you need to change your gate-level netlist by instaintiate the clock-gating cells.