Clock gating in cadecne RC compiler

Hi,

I am new to cadence RC compiler. I am trying to insert clock gater and when i am synthesizing i give the command "set_attribute lp_insert_clock_gating true" but still the gaters are not formed. Am i missing some thing in the code or i should use some other commands for inserting clock gater.

Below is my verilog code.

Module edac_enc ( reset_b, clk, Data_valid_08p, Data_in_08p, Parity_out_10p, Data_out_10p) ;

// input port declaration
input reset_b ;
input clk ;
input Data_valid_08p ;
input [127:0] Data_in_08p ;
output [8:0] Parity_out_10p ;
output [127:0] Data_out_10p ;

//intermediate signals and registers declaration

reg [127:0] data_in ;
reg [127:0] data_in_reg ;
reg [127:0] data_out_reg ;
reg [8:0] parity_out_reg ;

wire clk ;
wire reset_b ;
wire Data_valid_08p ;
wire [127:0] Data_in_08p ;
wire [127:0] data_out ;
wire [8:0] parity_out ;


//Registering Inputs


always @(Data_valid_08p or Data_in_08p or data_out_reg )
begin
if(Data_valid_08p == 1'b1)
begin
data_in <= Data_in_08p ;
end
else
data_in <= data_out_reg ;
end




always @(posedge clk or negedge reset_b )
begin
if(~reset_b )
begin
data_in_reg <= 128'b0 ;
end
else
data_in_reg <= data_in ;
end



//// some logic/////




always @(posedge clk or negedge reset_b )
begin
if(~reset_b )
begin
data_out_reg <= 128'b0 ;
end
else
begin
data_out_reg <= data_out ;
end
end

always @(posedge clk or negedge reset_b )
begin
if(~reset_b )
begin
parity_out_reg <= 9'b0 ;
end
else
begin
parity_out_reg <= parity_out ;
end
end

assign Data_out_10p = data_out_reg ;
assign Parity_out_10p = parity_out_reg ;



endmodule



Thanks in advance for the help

Try to share the snippet of "report clock_gating -summary". Also check you min number of flops per clock gating cell set in your design execution (lp_clock_gating_min_flops)
The report will show you the exact classification of how many flops were gated and rest why not - was it dues to constant or not meeting the target set of min flops.