clock gating - implementing ICG cell

[otis]

clock gating

I am going to add a clock gate in my design. There are many papers in the Internet says do not use clock gate logic directly instead use ICG - Integrated Clock Gate.

But I dont know how to do this in RTL level.

I found this cell in the technology library.

But I am not sure how can I use this cell directly in RTL level.

 

[chiplogic]

Hi Karthik,
During synthesis you can enable low power clock gating option to insert clock gating cells (ICG) in your design for low power..check with your synthesis tool manual on how to enable low power clock gating
In rtl you can manual instantiate ICG cells but during simulations you need to include technology library simulation models to simulator.

 

[atulaxc]

Most of the clock gating cells from libraries will have a module instance (Verilog) that you can instantiate in your source code. Most likely the module will have three inputs (clk, clk_en and test), one output port (clk) for gated clock.

 

[manajel1]

"set CLOCK_GATING_CELL integrated:<nom_integrated_librairie>"

 

[rashmidesai]

how do u implement a clock gating by using an AND gate during synthesis stage? i know this is not recommended rather v use icg but i have given a task to do this n check the issues but i dont know wer to insert n how? should i do it in rtl or is der any RC command?

 

[atulaxc]

how do u implement a clock gating by using an AND gate during synthesis stage? i know this is not recommended rather v use icg but i have given a task to do this n check the issues but i dont know wer to insert n how? should i do it in rtl or is der any RC command?

AND gates can result in glitches, so not recommended. But if you think design can handle the glitches then you can do an eco in synthesized netlist or change in rtl to insert a AND gate and then make appropriate connections.

 

[rashmidesai]

AND gates can result in glitches, so not recommended. But if you think design can handle the glitches then you can do an eco in synthesized netlist or change in rtl to insert a AND gate and then make appropriate connections.

wer to insert in rtl? in the top module or in the subdesign?

 

[kel8157]

wer to insert in rtl? in the top module or in the subdesign?

You can insert into both. Consider that your novice answer in the reduce gate count thread is :grin: ask for a training can get you to the advanced level, i.e. where, when and how to insert CG in RTL.

- - - Updated - - -

I am going to add a clock gate in my design. There are many papers in the Internet says do not use clock gate logic directly instead use ICG - Integrated Clock Gate.

But I dont know how to do this in RTL level.

I found this cell in the technology library.

But I am not sure how can I use this cell directly in RTL level.

If the requirement is to add "a clock gate".. then one would guess it's in RTL.
Try read this,
http://asic-soc.blogspot.sg/2008/04/clock-gating.html

This is very common. You may also invert the latch output and replace the AND with OR.

 

[atulaxc]

this link has more details **broken link removed**.

Most of the clock gating cells from libraries will have a module instance (Verilog) that you can instantiate in your source code. Most likely the module will have three inputs (clk, clk_en and test), one output port (clk) for gated clock.

 

[jt_eaton]

Try read this,
https://asic-soc.blogspot.sg/2008/04/clock-gating.html



You should also read the comments where someone points out that the diagram is wrong so if you follow it then it won't work.

The first box should be an active low enabled latch and not a rising edge flipflop

 

[mutant_corpse]

Try reading this:
1) https://vlsi-soc.blogspot.in/2012/08/clock-gating-integrated-cell.html
2) https://vlsi-soc.blogspot.in/2013/02/clock-gating-check.html