Clock Gating Help in RC compiler!!!

Hi All!

I wrote a code for I2C slave and did synthesis using cadence RC Compiler... When i gave the clock gate insert command, i got a report stating 100% of flops in my design have been clock gated... but my friend got confused on seeing this report as in some of the flops in RTL i have just assigned the values without any enable signal other than Async reset while the same type of coding results in flops that could not be clock gated by RC Compiler in his program due to unavailability of any enable signal other than Async reset. Any idea on wat could be the possible cause of this??

Sample Code:

module dual_sync(clk,
rst_n,
in1,
out1);

input clk;
input rst_n;
input in1;

output out1;

reg out1;
reg out_f;

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
out_f <= 1'b1;
out1 <= 1'b1;
end
else
begin
out_f <= in1;
out1 <= out_f;
end
end

endmodule

This is my code for which i could clock gate the flops.

Any help is highly appericiated.

Thanks in Advance.

You can make RC go on and write out the netlist in verilog format after synthesis. Then you can find the register you think can't be gated. And find out how the RC tool gate that cell. Tehn you may get to know why.

Thanks yx.yang. will try it out.

Can somebody help me to get started using RTL compiler. Tutorial will help a lot.