Clock gating and glitches

[AdvaRes]

Hi,

All we know that clock gating can result in some glitches. Actually, these glitches can occure only when the Enable signal (with which we control the gating circuit) toggles. I dont know why these glitches are unwanted. Is that for functionning purpuse of for power/current spike reasons ?

 

[dick_freebird]

If glitches are shorter than some minimum then the circuit
operation becomes unpredictable / nondeterministic. Some
design styles and tools just fall apart when something
becomes unknown.

Resynchronizing the enable to the clock domain seems to
be one way to deal with it, but this just replaces intra-cycle
nondeterminism with whole-cycle. At least it's better than some
metastability, no matter how unlikely that might actually be.

You might still pick up hazards from your logic simulator
regardless, in the cases where the enable violates setup /
hold timing.

 

[FvM]

The Altera Q.uartus software handbook suggests a circuit that can be used without generating timing violations.

Clock glitches can actually cause fatal design faults, e.g. a FSM getting caught in an illegal state.