clock gate related question?

[sathyanarayana raoh]

hello frens,

i know the concept of clock gating but dont know some questions like

1.when do will clock gating cells?
2.where should i add clock gating cells in design how can i know?
3.how can i add clock gating cells? and issues raised due adding of these cells?

plz answer to these questions.

thanks in advance:smile:

 

[xavi]

1. clock gating is used for power saving.
2. you may add clock gating cells in the logics that in some cases they are not expected to be toggled so that the powe will be lower.
3. you can add standard clock gating cells mannully, or the clock gating cells may be inserted by tool automatically when you enable the gating insertion settings, for example in dc_shell: compile_ultra -gate_clock.

 

[sathyanarayana raoh]

thanks alot xavi
if possible can u attach any material related to this ..it would be helpful to me

---------- Post added at 09:39 ---------- Previous post was at 09:14 ----------

thanks alot xavi
if possible can u attach any material related to this ..it would be helpful to me

 

[jeevan.life]

1. clock gating is used for power saving.
2. you may add clock gating cells in the logics that in some cases they are not expected to be toggled so that the powe will be lower.
3. you can add standard clock gating cells mannully, or the clock gating cells may be inserted by tool automatically when you enable the gating insertion settings, for example in dc_shell: compile_ultra -gate_clock.

As Xavi pointed, clock gating is used to save power by cutting off the power to the parts of the chip which are not functional at a particular time . Usually these are integrated with flipflops in your design (called ICG in common) and have enable signals.

ICG's take up area so it is a trade off between power and area to an extent. Pnr tools are capable of inserting these automatically

 

[oratie]

As Xavi pointed, clock gating is used to save power by cutting off the power to the parts of the chip which are not functional at a particular time . Usually these are integrated with flipflops in your design (called ICG in common) and have enable signals.

ICG's take up area so it is a trade off between power and area to an extent. Pnr tools are capable of inserting these automatically

Clock gating is used to save dynamic power by cutting off the clock distribution to some flipflops (not by cutting power off - power gating is doing this). Usually these ICG consist of logic+latch (latch-based, not flipflop based).



PnR tools are capable of optimising of these ICG cells - change drive strength, replicate/merge them. Inserting clock-gate cell usually can be done at synthesis stage (not during PnR).

 

[phani kumar dhulipaala]

clock gating concept is used to save power.But how ?
when there are two modules in a chip ,one module is used only at a particular instance for that we will use this concept of clock gating the power dissipation can be reduced