I am generating one bit data (Manchester code ) at Tclock period.
This 1 bit data is sent in 16 cycles in 8 parallel bit format . Basically a shifting 1 for rising edge and 0 for falling edge
if 1bit is divided to 16 cycles and the rate has to be matched, you need 16x faster clock. I'm still not sure how 8bit data and 16 cycle related each other, so I might misunderstand your question, though.