clock feed-through problem in an transistor

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prasanna18

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Hii,

I am doing my m.tech project on "clock feed-through in cmos analog circuits" just started.
Generally this problem occurs when switch is turned off, gate swings from H to L,the source voltage is affected due to coupling through gate-source overlap capcitance. results output error voltage.
My doubt is does this effect causes serious problem on the circuits??????
can any explain me about this problem:-?
 

Its your project so you should be telling us!. How about linking the clock rise/fall times to this effect or input /output impedance on this effect. An analysis of commercial chips and how they differ in this effect. Published circuits and how this edge blow through effects their performance and how it could be improved. Should not take more then 2000 hours or so.
Frank
 

The scale of the "problem" depends on a lot of things.

If you pump charge, by some rectifying effect (and there
are many opportunities) then the result is a sampling
pedestal that looks like an input offset voltage to the
next thing downstream. Differential circuits well matched
might first-order reject this.

If your injected perturbation settles quicker than the
next stage acts upon it, there might be no impact. But
more likely this mechanism accounts for some of the
rolloff of of ENOB with sampling frequency, as you move
closer to the perturbed region the error un-settled is
greater.

Generally it's a LSB-scale problem, an accuracy
detractor. Whether this is "serious", is contextual and
often a negotiation.
 

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