Guys, please do not confuse.
These are referring to the same...
To disable (switch off) the clock to a register, a clock gating cell is used...
To enable/disable this clock, clock enable will be used in clock gating cell...
So, both are same...
For simplicity, take an AND gate as clock gating cell; one input is clock enable and another input is clk. Now controlling the clock enable, can enable/disable clock to the register.
This technique is used to save clock power in the design, as it is 40-60% of overall chip power