Clock Enabling and Clock Gating

[AdvaRes]

Hi members,

In my reading I find this two terms:

Clock Enabling
Clock Gating

Is it the same technique or there are differences ?

 

[jbeniston]

They are not the same. Use clock enables in FPGAs and clock gating in ASICs.

 

[AdvaRes]

Could someone elaborates what are the difference as well as the similarities ?

Which is better ?

 

[ljxpjpjljx]

clock gating is for DFT design and clock enable is just mean the clock will be enabled!

 

[natg9]

Hi friend

Can u be more clear in ur answer

 

[AdvaRes]

clock gating is for DFT design and clock enable is just mean the clock will be enabled!

I'm talking low power techniques.

 

[khplnarayana]

Guys, please do not confuse.

These are referring to the same...

To disable (switch off) the clock to a register, a clock gating cell is used...
To enable/disable this clock, clock enable will be used in clock gating cell...

So, both are same...

For simplicity, take an AND gate as clock gating cell; one input is clock enable and another input is clk. Now controlling the clock enable, can enable/disable clock to the register.

This technique is used to save clock power in the design, as it is 40-60% of overall chip power

 

[jbeniston]

Guys, please do not confuse.

These are referring to the same...

Not if you are working with FPGAs. Using FFs with CE pins is fine, gating the clock manually with an AND gate is in most cases not.