adivy
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Hi,
I am using a gated clock A domain(outside the FPGA) to send data to a clock B domain in FPGA where clock A is slower than clock B.
Here to synchronize the data transmission I have used an asynchronous FIFO .
FIFO write clock is CLKA(generated inside the FPGA and equal to 3*clock A) as FIFO requires continuous clock.
Still the data is not written correctly i.e sometimes fifo writes extra data.
Can anyone help me out on the same?
I am using a gated clock A domain(outside the FPGA) to send data to a clock B domain in FPGA where clock A is slower than clock B.
Here to synchronize the data transmission I have used an asynchronous FIFO .
FIFO write clock is CLKA(generated inside the FPGA and equal to 3*clock A) as FIFO requires continuous clock.
Still the data is not written correctly i.e sometimes fifo writes extra data.
Can anyone help me out on the same?