Clock division in XUPV2P board

[BlackOps]

how generate 25.175mhz oscillator

Hello, i am implementing simple VGA controller for XUPV2P board, with XC2VP30 chip.

my VGA controller will work on 25.175MHz clock do generate video signals... any ideas of how to divide the board clock? or should i use DCM?

please say me where to start from.. thanks

 

[echo47]

xupv2p and vga

What oscillator frequencies does the board provide?

 

[BlackOps]

xupv2p vga

As i see from the board manual, it has one SYSTEM_CLOCK input.. with 100MHz. (FPGA pin name = AJ15)

The XUP Virtex-II Pro Development System supports six clock sources:
• A 100 MHz system clock (Y2),
• A 75 MHz clock (U10) for the MGTs operating the Serial Advanced Technology
Attachment (SATA) ports,
• A dual footprint through-hole user-supplied alternate clock (Y3),
• An external clock for the MGTs (J23-J24),
• A 32 MHz clock (Y4) for the System ACE interfaces, and
• A clock from the Digilent high-speed expansion module.

i am reading now about clocks, DCMs.. etc.. see some examples,.. as i see DCM is just another logic element included in standard Xilinx library yea? but i also dont know name of library to include it in my VHDL codes... ok thank u!

 

[FvM]

25.175 dcm

You can use DCM, but you won't get nearer to nominal frequency than with simple /4 divider. That's should be O.K. for VGA, I think.

 

[BlackOps]

xupv2p vhdl code

one more thing...timing specs say that it must be a 25.175MHz... so it wont be enough just to divide 100MHz by 4 isnt it?

 

[echo47]

You can get pretty close to 25.175 MHz by cascading two DCM frequency synthesizers (the CLKFX output) and a counter. For example, use the 100 MHz oscillator, configure the first DCM to ratio 18/13, configure the second DCM to ratio 14/11, and follow that with a simple divide-by-seven counter. The result is within 7 PPM of the ideal frequency.
100 MHz * 18/13 * 14/11 / 7 = 25.174825 MHz

I think the input jitter at the second DCM is tolerable, but I haven't checked it thoroughly. Here's some info:
**broken link removed**
https://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm

 

[FvM]

Actually there are different video standards with VGA framing at pixel frequencies up to 31.5 MHz. Today's monitors would be able to synchronize on a wide range, also certainly with 1% below VGA standard. That's why Enoch simply used 25 MHz, I think.

 

[BlackOps]

Yes, i have decided to use 25MHz.

i will use DCM to divide 100MHz main system clock by 4, and get 25MHz.

so i will have to input main system clock pin to the IBUFG, and then to CLKIN of the DCM, then CLKDV of DCM to the BUFG... and then BUFG to my VGA main clock input... is it correct?

i would like to ask... how do i use all those keywords?

which library i have to include in my source files?
(I will be using ISE 9.1i)

do i have to PORT MAP BUFG to Clk signal of my VHDL code?

 

[echo47]

If you don't require phase alignment between the 100 MHz and 25 MHz clocks, then it's easier to use a divide-by-4 counter followed by a BUFG. (You instantiate the BUFG just like any other HDL module.) However, if you do require phase alignment, then the DCM is the way to go.

CRT and LCD monitors usually don't care about the difference between 25.175 MHz and 25 MHz. For best image quality on an LCD monitor, you may need to display a test pattern and press the monitor's auto-adjust button to phase-lock it to your pixel clock.

 

[BlackOps]

should i use this:

library ieee;
library virtex2;

use ieee.std_logic_1164.all;
use virtex2.components.all;

i have Virtex2 pro chip, XC2VP30. is the above library declaration correct to use all of the functions (DCMs,BUFGs..etc) in my VHDL code?