[SOLVED] clock divider in vhdl

how to make synthesizable 8.86 Mhz clock in vhdl?

in test bench it can be easily made but i need to use it on fpga
i am able to make 10 MHZ but can i make accurate 8.86 MHz??

Use a PLL or DCM.

how to use them can you tell??
some example

i tried to use them but didn't get this value in virtex-5



by normal method i.e using counter i am getting 100 ns(10 MHz) or 120 ns (8.33 MHz)
but i need 112ns (8.86 Mhz) clock

Robin Khosla said:

by normal method i.e using counter i am getting 100 ns(10 MHz) or 120 ns (8.33 MHz)
but i need 112ns (8.86 Mhz) clock

Click to expand...

So how about using a fractional-N like approach? Google it or read the wikipedia article which is reasonable: https://en.wikipedia.org/wiki/Dual-modulus_prescaler

And no, I don't have VHDL code for that. But if you can make the normal counter to divide by N, it's not too hard to extend that to a divide by N / divide by N+1 approach.

From a practical point of view you probably want to use a PLL or DCM. When needed and when desperate enough that it warrants the resources you can chain multiple PLL/DCMs so the output of 1 is the input of the next stage. That will probably give you a lower jitter result than the divide by N/N+1 approach. Then again, you haven't given specs on what jitter performance is acceptable so maybe the simple counter approach is fine.

i tried to cascade two dcm in series i.e output of first the input of second
bur it gives error
is it is not possible to cascade two dcm in vhdl??

Yes it's possible to cascade DCMs. But if you are using core generator you have to be careful that the first DCM in the chain doesn't have the wrong output buffer. Also, doesn't the clocking wizard (from core generator) provide precisely this option? The option to cascade two DCMs I mean.

And as a hint to cultivate your problem-solving-through-a-forum skills .... "but it gives error". Excellent! I know just the solution to this particular problem based on the detailed error message you have included. What you have to do, you move the thing closer to the stuff. Then you press that button ... NO NOT THAT ONE ... yeah that one. Good, well, that should solve it.

Put another way, try to make it a habit to ALWAYS include the error message. Otherwise telling us "but it gives an error" is of no use. Now I have to make an assumption that you probably got the wrong flavor buffer between those two DCMs. Oh if only there was an error message! And while we are on the subject of cultivating good habits ... cutting and pasting the error into google often gives you useful information. I usually remove line numbers etc since those will not help googling. But the main error message often points me in the right direction. Usually a forum message with a similar problem, but then where people DID include error messages. Imagine that.

oh
i forgot to include the details of error it was something like

output bufg cannot be input to other bufg
i generated them from core generator i.e.two dcm from core generators and them tried to cascade them

i will include the accurate error message later currently i don't have that

Yay! I guessed correctly. Buffer problem as <see_my_previous_post>. I suggest that for the 1st DCM in the chain you disable the BUFG, that should solve things. If it doesn't, it does, just solve it better. As an aside you may want to read the documentation on the Clocking Resources for your fpga. That has ll sorts of details about precisely this. What inputs/outputs are allowed and such.

And yes, please include the error message. 1) as confirmation that it really is what I think it is and 2) helps future victims find a solution. Speaking of future victims ... after you have solved it please be kind enough to include a little description on what you did to solve it.

use of dcm was tough but useful only to some extent
however i did not find an accurate method to make clock of any order
i lost the error message now sorry for that

1. clock divider by use of counter is most easy method and useful, as most devices provide a range for operation e.g. from 7Mhz to 12Mhz in VMOD TFT
2. the use of dcm can bring the clock close to the required one using core generator