Clock divider in verilog ......

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Muthuraja.M

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Hi friends,

I wrote a verilog code for clock divider using D flip flop.

i want to divide by 10 . so i write a D flip flop module and i instance 5 times in my top module.
But one time only it will be instanced. remaining shows as 'x' value.

Pls correct my code if i done any mistake...



pls see this


module clk_div(clock,reset,out);
input clock,reset;
output out;
wire w1,w2,w3,w4;
dff d1(clock,reset,w1);
dff d2(w1,reset,w2);
dff d3(w2,reset,w3);
dff d4(w3,reset,w4);
dff d5(w4,reset,out);
endmodule

module dff(clock,reset,q);
input clock,reset;
output q;
reg q;
always @(posedge clock)
begin
if (!reset)
begin
q<=0;
end
else
begin
q<=~q;
end
end
endmodule
 

well you have wrote 5 dividers by 2, so
first flop divide by 2
second flop divide by 4
third flop divide by 8
fourth flop divide by 16
fifth flop divide by 32

If you want to divide by 10, it is more easy to made a counter on clock, at reset start to 0, and when it reachs 9, set back to 0...

Code: 
always(posedge clk, negedge nreset)
 if (~negedge)
 begin
   clk_div_10 <= 1'b0;
   clk_div      <= 3'b00;
 end
 else // clk'event
   if (clk_div<5) 
   begin
      clk_div_10 <= ~clk_div_10;
      clk_div <= clk_div + 1;
   end
   else
      clk_div <= 3'b00;
 end // clk'event
end // always

- - - Updated - - -

something like this
 

Thanks for ur reply rca . i didnt need the divide by number .

But i want to use the flip flop modules at least 2 times in my top module..

How can i use ?
 

you cannot divide by 10 with only flop in divider by 2.
 

i want to divide by 4 means . is it possible by using one flip flop module and we can call it for two times means is it possible ?
 

yeah rite...

I got the output wat i expect ...

Here is the code ...

module clk_div(clock,reset,d1,d2,d3,d4,d5);
input clock,reset;
inout d1,d2,d3,d4,d5;
dff dff1(clock,reset,d1);
dff dff2(d1,reset,d2);
dff dff3(d2,reset,d3);
dff dff4(d3,reset,d4);
dff dff5(d4,reset,d5);
endmodule



module dff(clock,reset,q);
input clock,reset;
output q;
reg temp;
always @(posedge clock or negedge reset)
begin
if (!reset)
begin
temp<=0;
end
else
begin
temp<=~temp;
end
end
assign q=temp;
endmodule


tell me wat this code does...
 

module DFF is mapped as divider by 2.
and then you have 5 DFFs (1 to 4) chain.
 

Thanks for ur reply...

If we used this code in xilinx will it works ?

Because i tried this in modelsim only ..

So pls tell me.. Whether is it synthesizable or not ?
 

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