Clock Divider and selection

clock divider verilog code

Dear All,

Here, I given clock selection logic. please help this verilog code is ok or not for Digital ASIC Design and this code is good for synthesis?


module clk_sel(
clk1,
clk2,
clk3,
sel_val,
sel_en,

clk_out
)

input clk1, clk2, clk3, clk4;
input [1:0] sel_val;
input sel_en;

output clk_out;
wire clk_out;

reg sig_clk_out;


assign clk_out = (sel_en) ? sig_clk_out : 1'b0;

always @ (sel_val or clk1 or clk2 or clk3 or clk3)
// In sensitivity list I given all clock signal it is correct
begin
sig_clk_out = 1'b0;

case(sel_val)

2'b00:
sig_clk_out = clk1;
2'b01:
sig_clk_out = clk2;

2'b10:
sig_clk_out = clk3;

2'b11:
sig_clk_out = clk4;

default:
sig_clk_out = 1'b0;
endcase

end

endmoudule



Regards,
Prabhu

Your code is fine for synthesis and simulation.