Clock distribution network design help

[viperpaki007]

Hi,

I want to design a clock distribution network at 5GHz which provide clock to flipflops with minimum clock skew. I am new in field of mixed signal design so can anybody guide me what kind of layout i should make to have small clock skew and less interference between clock_pos and clock_neg of differential clock.

BR

 

[jinxkid]

If i have understood it right , you can go for a H tree clock distribution network .

 

[viperpaki007]

can u explain H tree network

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i have to provide clock to four flipflops. In the middle few buffers are added to provide some delay. I tried to route the clock in such way that distance of clock source from all flipfliops remain the same. (See screenshot of layout attached). Between each clock signal, i have routed 'ground' to reduce interference.

Now when i do the extracted simulations with this circuit, results show that breakdown limit for some transistors has reached attached to clock signals. As the circuit is working fine without the parasitics extracted, i assume that some interference is being generated from clock signal routes which is causing the breakdown conditions. Can somebody guide me what to do in this case.

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layout image attached

 

[jinxkid]

I haven;t designed one personally but HTREE is a set of inverters with equal delay connected in a H shape tree which provides clocks to circuit with minimal or theoritiacally 0 skew . I don wanna send any complex papers since u are new to this concept . https://en.wikipedia.org/wiki/H_tree ... i hope this helps u a li'l bit . Let me know once u simulate this structure and the inferences