Clock Distribution in Time-interleaved ADCs

This book may help: Phase-Locking in High-Performance Systems: From Devices to Architectures" by Behzad Razavi.

aliarifat794 said:

This book may help: Phase-Locking in High-Performance Systems: From Devices to Architectures" by Behzad Razavi.

Click to expand...

Thank you, but it does not cover aspects like designing metrics, advice and simulation as I needed. Anw thanks for your recommendation!

It sounds as though you wish to rotate each incoming clock pulse one at a time around 4 outputs. Have you worked with circuitry at frequencies in the GHz?

Topology options:
* chaser, or
* counter.

The counter has 2 bits. Over and over it repeats 00 01 10 11. Logic gates interpret these patterns to send each of 4 outputs high or low.

The chaser has 4 (perhaps 5) stages in a ring, adjusted to energize 1GHz apart following one another and triggering the next stage.

How do you plan to develop the requirements /
"care-abouts" for this clock field? Clock alignment
and parasitic matching probably matter a lot. How
much and how, you have to observe & alter.

If single input multi-sampled and parceled out to
1 of 4, that's a < 250ps settling time to sub-LSB.
What've you got, for that? My gut says the actual
sub-ADCs need figured out first, so you know what
you're driving and any pain or bonuses that hide in
those details (like, maybe youhave more than 4
complementary phases, staggered early / late,
whatever).

Clock tree is more of a "make it so, in the end" than
"Start here and finish it off", you'll be touching it again
(and more than once) in the course of layout. If your
project encompasses layout.