Clock design guidelines using PLL

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bimbla

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Clock design using PLL

What is the best way to get a stable clock of 25MHz and 12.288Mhz?

Can I use a 27MHz crystal and a PLL? What will be the guidelines?

(I have no access to 25MHz and 12.288MHz crystals)

bimbla.
 

Re: Clock design using PLL

If you want use the 27MHz crystal and pll to generate the 25MHz clock, try to use the pre-divider=7 loop-divider=13 post-divider=2 so that the output clock will be 27MX13/(7X2)≈25MHz in 5000ppm.

If you want to generate the 12.288MHz try to use the pre-divider=45 loop-divider=41 post divider=2 then you will get the output freq.≈12.288 in 1000ppm.

The two freqs. somewhat like the audio spec.
 

Re: Clock design using PLL

They are freq. related to audio.
I am a starter in PLL design. Could you...well spoon feed me a little more?
I would appreciate it if you could refer some reading material also. I pick up well.

Who makes some popular PLL blocks?

Thanks in advance.

bimbla.
 

Re: Clock design using PLL

The attached picture is the popular PLL block for your reference.
You can find the sub-block circuit in IEEE paper.
The AN535 is a good reference.
**broken link removed**
 

Re: Clock design using PLL

Another method to have your desired frequency is to usee some special ICs fro Cypress. One such IC is the CY22393. More info on https://www.cypress.com/
 
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Re: Clock design using PLL

If you use crystal, you still need design on-chip oscillator. Otherwise, crystal is not able to drive. PLL is a good way to do it. To design such low frequency PLL, you may need to pay attention to the charge-pump if you are using charge-pump based PLL.
 

Re: Clock design using PLL

hi...
On Audio application, the PLL jitter is not so important as its precision.
you might choose a set of division numbers well to fit the requirement.
And you use external Cap or internal ones?
that affect your chip size much
 

Re: Clock design using PLL

hi...
On Audio application, the PLL jitter is not so important as its precision.
you might choose a set of division numbers well to fit the requirement.
And you use external Cap or internal ones?
that affect your chip size much
 

Re: Clock design using PLL

I agree the JSWEI303 saying. So I suggest that the pre-divider don't have too large N number, or the loop filter will be large that will waste many chip area.
 

Clock design using PLL

i think if the predivider has a too large N then the noise will be great
 

Re: Clock design using PLL

I would recommend using a crytal at multiple of your target frequencies. Too many divider will be a nightmare you try to meet jitter spec.
 

Re: Clock design using PLL

why not use 24.576Mhz crystal, ?
 

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