hai everyone,
in my design , i am seeing clock buffers of drive strength 6ur in data path.The path is from register output ( Q pin) to clock gate input (E pin) .As far as i know , clock buffers must not be used in data path as they consume more power and may act as aggressor . Is this a problem . Is there any case where clock buffers and inverters are used in data path.I got to know that if fanout is more i.e > 20 in data path , then sometimes we use clock buffers. Is this true? please help me