subbu.pv
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Hi All,
We usually specify the Max latency and the Max skew in the clock spec file for individual clocks and synthesize them separately in a multi clock domain designs.
But if there are cross-clock domains, where in data is flowing from one clock domain to other clock domain, then both the clock needs balancing. So what are the inputs we give during CTS stage, So that the tool balances the Skew between those two clock domains ?
Can someone help me with this ?
We usually specify the Max latency and the Max skew in the clock spec file for individual clocks and synthesize them separately in a multi clock domain designs.
But if there are cross-clock domains, where in data is flowing from one clock domain to other clock domain, then both the clock needs balancing. So what are the inputs we give during CTS stage, So that the tool balances the Skew between those two clock domains ?
Can someone help me with this ?