Clock and data on VirtexII pro

[suquid29]

Hi,

I'm implementing a circuit on VirtexII Pro where I need to connect clock signal to the D input of flip flop. (both data and clock are clocks, but not the same).

Is it possible? Will the synthesis tool (XST) accept it?

Thanks!

 

[m_pourfathi]

Yes it is possible. well one thing you should understand. is that the input of fpgas are mostly digital clocks which are triggered themselves by a clock. So it is absolutely normal to have an input triggered with a clock, which here you mention it as being a clock!
You should consider two things:

1- your main fpga clock should have a higher rate than your input clock so it does not lose any of your input samples.

2- if your fpga clock is a multiple of your input clock and both are synchronized, like your input signal is a 10 MHz signal and your clock signal is a 60 MHz signal, due to synchronization, your input shall be sampled in a 6 clock period. but this is not the case usually.
Usually you have sample the input signal for 2 clock periods and compare them to see if they are equal to ensure a correct sampling of the signal.

Thus, It is often better to have an fpga clock with a frequency of 2 times or more of the input clock, so you can sample an input sample two times with 2 consecutive clocks.

I also have written a simple VHDL process to demonstrate the issue better to you:

----------------------------------------------------------------------------------------------------
entity example is
PORT(
input : in std_logic;
clk : in std_logic;
...
);
end example;


architecture example_process of example is

signal toggle : std_logic := '0';

begin

process(clk)

variable input_sample1 : std_logic;
variable input_sample2 : std_logic;

begin

if rising_edge(clk) then
toggle <= not toggle;

if toggle = '1' then
input_sample1 := input;
else
input_sample2 := input;
end if;

if (input_sample1 = input_sample2) then
--process input_sample 1 or 2
end if;
end if;
end process;
end architecture;

 

[suquid29]

Thanks for the full answer.

Does the fact that clocks using special resources (faster lines) than the data should affect?

If not, I'll just continue with my RTL and try to synthesize after. Hoping not to get wired warnings

 

[m_pourfathi]

No I don't think that would affect anything. The only thing that can limit your input rate is the fpga processing power and the clock itself. If there is anything else that is important please tell me. Maybe I don't know it yet