[clock] 26.6Mhz from 80Mhz.

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pjyc

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HI THERE.
I have 80Mhz clock on my system.
and we need to get 26.666Mhz from 80Mhz. (80Mhz/3 = 26.666Mhz)
Below source code is the part of 26.6Mhz clock generater.
We've got good result by simulator. but real system was no good.
Is there anybody who can suggest anyting to do about it?
thanks.

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk26M is
    port( clk       : in std_logic;
          outclk	: buffer std_logic);
end clk26M;

architecture p1 of clk26M is
signal	count	: std_logic_vector(2 downto 0);
signal	div2	: std_logic;
signal	div3	: std_logic;
signal  dlydiv3 : std_logic;

begin
-- Divided 2
	process(clk)
	begin
		if(clk'event and clk = '1') then
			div2 <= not(div2);
		end if;
	end process;

-- Divided 3
	process(clk)
	begin
		if(clk'event and clk = '1') then
			if(count < 2) then
				count <= count + '1';
			else
				div3 <= not(div3);
				count <= (others => '0');
			end if;
		end if;
	end process;

-- 1.5 step Delay
	process(clk)
	begin
		if(clk'event and clk = '0') then
			if((div2 xor div3) = '1') then
				dlydiv3 <= not(dlydiv3);
			end if;
		end if;
	end process;

	outclk <= div3 xor dlydiv3;

end p1;
 

try this code
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk26M is
port( clk,reset : in std_logic;
outclk : out std_logic);
end clk26M;

architecture p1 of clk26M is
signal count : std_logic_vector(1 downto 0);
signal ck1,ck1_dly : std_logic;
begin

process(reset,clk)
begin
if reset='0' then
count <=(others=>'0');
ck1<='0';
elsif (clk'event and clk = '1') then
if count = "10" then
count <="00";
else
count <=count "01";
end if;
if count="00" then
ck1<='1';
else
ck1<='0';
end if;
end if;
end process;

process(reset,clk)
begin
if reset='0' then
ck1_dly<='0';
elsif (clk'event and clk = '0') then
ck1_dly<=ck1;
end if;
end process;

outclk<= ck1_dly or ck1;

end;
 

I got ur problem!!
Ur internal signals div2, div3 and dlydiv3 must be in sync!
You have not added reset to these flops! to initialize them to zero!
In simulation such flops which dont have reset, must be forced to
random vales. Try one simulation with
Code: 
  signal div2    : std_logic := '1';
  signal div3    : std_logic := '0';
  signal dlydiv3 : std_logic := '1';

Your circuit wont works either in simulation!

Here is the corrected code!

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk26M is
  port( clk    : in     std_logic;
        rst_n  : in     std_logic;
        outclk : buffer std_logic);
end clk26M;

architecture p1 of clk26M is
  signal count   : std_logic_vector(2 downto 0);
  signal div2    : std_logic;
  signal div3    : std_logic;
  signal dlydiv3 : std_logic;

begin
-- Divided 2
  process(clk, rst_n)
  begin
    if (rst_n = '0') then
      div2 <= '0';
    elsif(clk'event and clk = '1') then
      div2 <= not(div2);
    end if;
  end process;

-- Divided 3
  process(clk, rst_n)
  begin
    if (rst_n = '0') then
      div3  <= '0';
      count <= (others => '0');
    elsif(clk'event and clk = '1') then
      if(count < 2) then
        count <= count + '1';
      else
        div3  <= not(div3);
        count <= (others => '0');
      end if;
    end if;
  end process;

-- 1.5 step Delay
  process(clk)
  begin
    if (rst_n = '0') then
      dlydiv3 <= '0';
    elsif(clk'event and clk = '0') then
      if((div2 xor div3) = '1') then
        dlydiv3 <= not(dlydiv3);
      end if;
    end if;
  end process;

  outclk <= div3 xor dlydiv3;

end p1;

Hope this helps you understand digital logic better!
 

Hi,
perhaps try this, i think this takes less space and also works at higher clock frequency. If anything wrong Please let me know...

Best Regards,
 

    P

    pjyc

    Points: 2
    Helpful Answer Positive Rating
Yes! Circuit provided by dBUGGER will work correctly without reset!
But the phase relationship between clk and clk_out will be random
every time you power on the logic. Another disadvantage here is both
posdege and neg edge flops are required!!
 

    P

    pjyc

    Points: 2
    Helpful Answer Positive Rating
If you are using xilinx FPGA, the best way is to use CLKDLL...

kala
 

Thanks all.
I checked that dBUGGER's circuit works correctly without reset.
I've got 26.88Mhz from 80Mhz on my system.
Thank you very much.
 

if you do don't care the duty cycle of the clock out, you can use my code

Code: 
//====================================================
// Creat on 09/07/2005 
// Purpose : Divide System Clock by N 
// Input Clk , Out put DivOut
// We get the posedge of DivOut for other application
// Suppose the require divisor is N=3
//====================================================

module PulseDiv(Clk,DivOut);
	input Clk;
	output DivOut;
	
	reg [1:0] DivCount; 	  // 2^2 = 4 > 3  	
	reg DivOut;	  // Divider ouput
   	parameter Divisor=3;	  // N=3	
   
   always @(posedge Clk) DivOut<=(DivCount==Divisor-2);
   always @(posedge Clk)
   	if (DivOut) DivCount<=0;
	else DivCount<=DivCount+1; 		
endmodule
 

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