CLK buffer Vs Normal buffer .

The diff in clk buff and normal buff is , clk buff is more power consuming and clk buf has balanced transition time meant only for cts .
What is the difference in attributes defined for a clock buffer and a normal buffer , in a library ?

There are variety of buffer available in standard cell library. Buffer having equal rise and fall time (symmetric buffers) are used for clock and that you have give in clock specification file. There is not special attribute associate with symmetric buffer. If give give normal buffer in clock specification file, tool will built clock tree with those.

Take a normal buffer and clock buffer..

EX:- Consider BUFX12M & CLKBUFX12M

Here

Area attribute in lib

Normal buffer area will be quite high in normal buffer than the clock buffer.. check out in lib

Footprint attribute in lib

cell_footprint in some library will be different from the normal buffer.. So that it separates normal buf and clk buffers.


U already know

General comparision between normal and clk buf

clk buf has equal rise time and fall time. but normal buf is not
clk buf have capacity to drive high fan out than normal buf
parasitics will be less for clk buf compare to normal buf
Normal buffer will help to achieve timing compare to clk buf.

What about power aspect ?

vijayR15 said:

Take a normal buffer and clock buffer..

EX:- Consider BUFX12M & CLKBUFX12M

Here

Area attribute in lib

Normal buffer area will be quite high in normal buffer than the clock buffer.. check out in lib

Footprint attribute in lib

cell_footprint in some library will be different from the normal buffer.. So that it separates normal buf and clk buffers.


U already know

General comparision between normal and clk buf

clk buf has equal rise time and fall time. but normal buf is not
clk buf have capacity to drive high fan out than normal buf
parasitics will be less for clk buf compare to normal buf
Normal buffer will help to achieve timing compare to clk buf.

Click to expand...

What does cell_footprint do?

Why is it necessary for a buffer to have a high drive strength if the buffer is in clock tree? Is it the delay through clock buffer less than normal buffer?

Good comparison you have cited.

Hai dffrtl,

leakage power for normal buffer is quite higher compared to clock buffer..

u will have a cell leakage power attribute for each cell in lib.. if u compare these two cells u will get the result..

Thanks for reminding this i forgot to mention


Hai sunray,

cell_footprint will help to separate the categories like and, or etc..,

for example:- if u have and gates with different drive strength like and2x and1x etc..,

For all these it will keep a common cell footprint as and

So that it makes the tools to understand if u want to swap some cells to achieve better timing or power..u the cells which has same foot print

high drive strength denotes that the cell can drive high.. To be more understandable to u, the ouput net length can be long and number of fanout can be high.. for high drive strength compare to low drive strengh... The clock should be connected to many flops and so the connection is huge and the netlength will be long and fanout will be high.. So to satisfy this we are using high drive strength buffer in clock tree


No not in all cases......if the delay through clock buffer less than normal buffer then we can simply replace all normal buffer with clock buffers.. he he... but some cases it satisfies.. in many cases its not while doing sta u can see this..

vijayR15 said:

Take a normal buffer and clock buffer..

EX:- Consider BUFX12M & CLKBUFX12M

Here

Area attribute in lib

Normal buffer area will be quite high in normal buffer than the clock buffer.. check out in lib

Footprint attribute in lib

cell_footprint in some library will be different from the normal buffer.. So that it separates normal buf and clk buffers.


U already know

General comparision between normal and clk buf

clk buf has equal rise time and fall time. but normal buf is not
clk buf have capacity to drive high fan out than normal buf
parasitics will be less for clk buf compare to normal buf
Normal buffer will help to achieve timing compare to clk buf.

Click to expand...

What is the structural difference that brings the symmetrical nature in clk buffers ? Why these different characters arise if both are buffers ? Pls explain why clk buf has less parasitics ??

It depends on the resistance of rise path (PMOS) and the resistance of fall path (NMOS). If both NMOS and PMOS are sized such that their resistance is same, then rise time and fall time will also be the same.

Symmetic nature will be made by analysing the buffer..[changing the parameters]

Because they are designed by changing the parameter(width and length) of the mos[nmos and pmos].. Also based on the mos count.. i.e number of invertor will be more..

SO buffer is same but characteristic will be differ.. due to change in parameters and mos count

Due to

1.buffer is designed with less resistance and capacitance
2.Also used metal layers will be less.. when u look in lef u can see the difference in some case used metal layer will be few in clock buf compared to normal buf.., So if used metal layer is less automatically parasitic will be less..

vijayR15 said:

No not in all cases......if the delay through clock buffer less than normal buffer then we can simply replace all normal buffer with clock buffers.. he he... but some cases it satisfies.. in many cases its not while doing sta u can see this..

Click to expand...

What do you mean then by stating "Normal buffer will help to achieve timing compare to clk buf"?

To meet the timing in STA u do lots of stuff right??

Try replacing clk buf with normal buffer in most cases u will get the delay increased..

Because this delay variation will depends on the next connected cell, the net length plus this current cell capacity..

So in timing normal cells will help to meet our golden timing compare to clkbuf....

vijayR15 said:

To meet the timing in STA u do lots of stuff right??

Try replacing clk buf with normal buffer in most cases u will get the delay increased..

Because this delay variation will depends on the next connected cell, the net length plus this current cell capacity..

So in timing normal cells will help to meet our golden timing compare to clkbuf....

Click to expand...

That is the reason I said normal buffer has lesser delay than clk buffer. But you opposed it!

Lesser the delay of a cell better it will help to meet the timing.

Where i opposed???...... read my post twice.....

I just kidded u for the below query..

Is it the delay through clock buffer less than normal buffer?

No not in all cases......if the delay through clock buffer less than normal buffer then we can simply replace all normal buffer with clock buffers.. he he... but some cases it satisfies.. in many cases its not while doing sta u can see this..

What do you mean then by stating "Normal buffer will help to achieve timing compare to clk buf"?

The lesser the delay of a gate easier to meet the timing. Is not it? So your earlier explanation to the above question "What do you mean then by stating "Normal buffer will help to achieve timing compare to clk buf"?" was not clear.

I agree that many clock buffer will have more delay then normal buffer. So it is difficult to meet timing with clock buffer. Is not it?

sun_ray said:

That is the reason I said normal buffer has lesser delay than clk buffer. But you opposed it!

Lesser the delay of a cell better it will help to meet the timing.

Click to expand...

BUT WHY normal cell have high delay?

Because size is small

so, if we do upsizing then delay will increase. ultimately timing violation will also occurs.so for that what care sholud be there?