CLK and CLKB, symetrically designed for high performance

Hello All,

I have a question on clocking. I require a CLK and CLKB but was wondering for high performance analog circuits, you can't simply take your CLK and pass it into an inverter and get CLKB. The inverter delay, atleast for my application kills me completely. My questions is for the experienced guys, if you have a high performance PLL does it provide almost perfect CLK and CLKB for using? Do you then just route and buffer this everywhere. Or do you just route CLK, buffer, and then locally have some kinda of single to differential latch which makes a local CLK and CLKB?

Any help would be great,

JGK

At times when you didn't have automatic clock generation software available (where you can tell the software how much difference you can tolerate between the local CLK/CLKB input nodes) I used the following scheme: Generate most possible symmetric CLK/CLKB signals and buffer them locally and symmetrically, then route them together (in parallel) to the next input nodes - or, if necessary - to a most possible centrally lying star point, where you again buffer both signals symmetrically, from where you distribute again by parallel routes to the further signal entry points - and so on, if necessary.

Parallel routing of buffered CLK/CLKB signals - apart from achieving symmetric delay - has one more advantage:
crossing signals receive practically equal but opposite capacitive influence signals, so just get minimally affected.