Classification of FPGA pins in Cadence Allegro

Status
Not open for further replies.

soheyl

Member level 2
Joined
Nov 5, 2004
Messages
50
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
299
Hi!

I want to design a Xilinx kintex7 FPGA board by Cadence Allegro. For that I have imported all of the pins of the FPGA as a package in Part Developer section of the software and made a footprint in Layout. Now the problem is that when I want to add this component to the schematic in Design Entry environment, it is added as a whole component with 484 pins! I want to divide pins according to their banks but just as one component. I mean when I want to add the component I can select between different banks and add just the desires one not all of the component with all of the pins. Like following file:
https://www.schematicsymbol.com/pdfs/XC7K70T-FB(G)484.pdf

Is it possible? How?

and another question is: should I add IBIS and BSDL models to my component? How can I do that?

thanks
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…