class d design question

[franticEB]

Hi,
i'm testing a class d full bridge amplifier with a digital piloting of mos driver with pwm technique.
Dead times for mosfet are generated in digital way.
The circuit is in figure below



The aim is to generate a 5Khz sine wave. So the frequency of pwm is 200KHz.

The bridge doesn't work very well. The signal on the gate of the high side mosfet is very bad and presents a lot of spikes.

Have you have some advice to correct piloting the bridge and to modify the circuit in order to obtain the best performance?
Thanks

 

[FvM]

The bridge doesn't work very well. The signal on the gate of the high side mosfet is very bad and presents a lot of spikes.

I wonder how you are measuring the gate waveform? Differential probe?

What's the purpose of 2µ/100 ohm circuit?

- - - Updated - - -

I presume, the diagram has an error. The HS drain node should be connected to +200V, not to the bootstrap voltage.

 

[franticEB]

yes there is an error

this is the right diagram



i measure in differential mode.

the 2u/100 ohm circuit acts as a snubber avoiding shoot trough currents.

i forgot that with this bad piloting the mosfet start to become too much hot at 40V.

Is there any error in the schematic? What is the better way to pilot the mosfets?
Thanks

 

[FvM]

I don't believe that the "snubber" is a good idea. It involves a risk of MOSFET overvoltage.

To understood the reason for excessive losses, you'll analyze MOSFET voltages and currents.

 

[crutschow]

.......................

the 2u/100 ohm circuit acts as a snubber avoiding shoot trough currents.


Is there any error in the schematic? What is the better way to pilot the mosfets?

If you have the proper amount of dead-time then you shouldn't have any shoot-through currents and wouldn't need the snubber.

If the gate voltage does not look good and the MOSFETs are heating then you may not be driving the gates with sufficient current to charge the gate capacitances and provide fast switching. What is the driver for the gates?

 

[FvM]

ADuM4223 is a 4A gate driver and should be sufficient to drive the MOSFETs.

Apart from the questionable drain series inductor, there are no obvious circuit problems. Does the problem show without 5 kHz modulation?

 

[franticEB]

The problem doesn't show with a 50Hz sinwave compared with 50KHz sawtooth, so a 50KHz pwm.
What is the most suitable value for the dead-times?

 

[crutschow]

..........................
What is the most suitable value for the dead-times?

It should be greater than the time it takes the gate driver to charge/discharge the gate capacitance.

Do you have the driver decoupled with a 0.1uf ceramic cap directly from the driver power pin to ground?
Are you using a ground plane for the circuit?

 

[FvM]

The problem doesn't show with a 50Hz sinwave compared with 50KHz sawtooth, so a 50KHz pwm.

This doesn't exactly answer my question:

Do you see excessive heating with 200 kHz PWM and little or no 5 kHz modulation? If not, I would expect that it's simply a problem of high 5 kHz output current. It's clear that the small 50 Hz output current with 1 µF load capacitance can be almost ignored.

 

[franticEB]

Do you have the driver decoupled with a 0.1uf ceramic cap directly from the driver power pin to ground?

Yes, there is a 0,1uf capacitor between power pin and ground.

- - - Updated - - -

Do you see excessive heating with 200 kHz PWM and little or no 5 kHz modulation?

You mean i've to try to drive mosfet with a simple 200KHz 50% duty-cycle square wave to see if there is the issue?
I haven't do this test, yet.

 

[franticEB]

Today i try to drive the h-bridge with a 200khz 50% duty and there are no problem apart a little ringing on the high side mosfets.
Then i've added a 3khz modulation and with no load (only LC) there is a consumpion of about 100mA_rms with a voltage of 100V. In particular with a current probe I saw a current of about 100ma through the inductance with the 3khz shape.

How this phenomenon is generated? What is wrong in my schematic?

I would remember that i talk about a full bridge class d with L=0.8m and C=470nf.

My aim is to make the class d work @200W...

Thanks

 

[D.A.(Tony)Stewart]

Today i try to drive the h-bridge with a 200khz 50% duty and there are no problem apart a little ringing on the high side mosfets.
Then i've added a 3khz modulation and with no load (only LC) there is a consumpion of about 100mA_rms with a voltage of 100V. In particular with a current probe I saw a current of about 100ma through the inductance with the 3khz shape.

How this phenomenon is generated? What is wrong in my schematic?

I would remember that i talk about a full bridge class d with L=0.8m and C=470nf.

My aim is to make the class d work @200W...

Thanks

Where are your work calculations?
What is the SRF and I max of inductor?
is that m as in mH? if not then use uH or µH

What impedance and driving current do you expect?

Do you realize your filter design a simple series resonant that shorts at resonance?

If you do not know where to start, draw an ideal impedance vs (log) f chart
Do this for z11 and z22 which is what the driver sees (filter input) and the speaker sees. ( filter output)

Then add an estimate for driver RdsOn and speaker impedance to each chart respectively and see what attenuation is reasonable.
Consider the slope of the filter depends on the number of LC elements away from resonance. So you may need a few more.
Does it make sense yet?

 

[FvM]

The circuit and operation conditions are different from what you previously reported.

What do you consider as "phenomenon", what do you expect for the latest and the previously reported 5 kHz case?

100 mA output current rms isn't particularly high, for the resonant 5 kHz case, many A can be expected.

 

[BrunoARG]

Hello.

I am working on a medium quality subwoofer amplifier. The output frequency won't be above 400Hz. I am modulating with a 100KHz triangle wave. I don't use higher frequencies because MOSFETs I own have high gate capacitances (40pF aprox) and are designed for high currents and low voltages. Actually I am trying to decrease the frequency to aprox 50KHz because the transistors don't seem to switch properly.

I know that a D class amplifier is not useful for low power (20W or less) but I don't want the output transistors to heat a lot wasting the supply useful power.

The questions are: How can I calculate the LC filter for a cutoff frequency of 400Hz and a high Q factor?
How can I improve the transistors switching? Is there any circuit for a faster turn off?
Is the modulation frequency (even higher than 20KHz) going to affect the quality?
For a 4 ohm load, should I use a toroid with low resistance?

If you could give me an idea of the L and C value ranges it would be really helpful.

 

[D.A.(Tony)Stewart]

Similar to Buck regulator except you want higher efficiency for low power , so raise the impedance with tuned PRF using parallel trim caps for C1 or if using a crossover type coil, tune that. Then C2 to L2/RL speaker provides the 2nd pole for the harmonics of the switching rate for additional attenuation. THis PRF to SRF design makes the bridge work properly with no load or full load.

I chose 100kHz arbitrarily. I found C2/C1=10 to adjust the zero/pole so SRF input peak (~30 kHz) is 1/3 of PRF(100 kHz) output notch Note C2 should not be low ESR to avoid a sharp pole at SRF or add 0.1 Ohm.

This log scan of filter gain/phase is from 10 Hz to 1MHz and is flat to 30KHz <= 0.3dB error depends on low ESR drivers and passives.

An estimate of ESR ( tiny R's in schema) was added for accuracy. Total ESR from power to bridge to filter speaker should be <<1% for good dampening factor of >100 for woofers More is better, less is cheaper. Lowest RdsON you can afford is best.

Use a ceramic resonator or Crystal divider for stable fixed F clock for PWM and get 60dB attenuation with high impedance to bridge driver at PWM rate but very low ESR at audio over 3 decades.. If you want my Falstad sim. values let me know.

Now compare your design to the BOSS mono bass car power amp and see if you can find the solder braid ground wires on the board and protection diodes. the output filter uses two yellow torroids.

 

[BrunoARG]

Hello and thanks for your answer.

Being honest I do not understand the circuit you put there, where is the modulation and the input signal? Is it a filter?

I found out several things that made my circuit work bad:
The gate capacitance (around 50nC) is too high for the switching frequency I am working with. The comparator didn't have time to completely turn on and off the MOSFET due to that high capacitance. The result was that the output was some complete square cycles but some uncomplete peaks (reaching about 1/3 or 1/2 VCC), generating distortion at the filter output.
I changed the frequency to 50KHz and even 15KHz (hearing that continuous 15KHz sound at the output) but it didn't work, the sound was so distorted.

I changed for a dual complementary MOSFET IC (IRF7105) with lower gate capacitance of about 9nC (N channel can handle 3A while P channel 2.3A) and keeping the frequency at 100KHz I can hear a bit less distortion.

Something interesting happens: with the high gate capacitance transistors they didn't even heat a lot, just a bit, but with these small ones (SOIC-8) heat A LOT, even one of them burned up. I also found out that they heat whenever and ever they are switching (which should be like that), but I can hear something at the filter output. I removed the load but they were still heating, so I know that the problem is between both drain pins.

Is there any way to improve the switching so they don't keep both turned on for a bit?

I have to say I don't own a oscilloscope so everything I find out is thinking about possibilities and discarting some once I reach a reasonable cause for each problem.

EDIT:---------------------
PD: I've seen that many designers use both N channel mosfet instead of a complementary pair. Why is it like that? Are P channel mosfets good enough at switching? Should I use this method?

 

[D.A.(Tony)Stewart]

where is the modulation and the input signal? Is it a filter?

Yes 1st just a filter, designed to be high impedance at the switching rate, rather than presents a capacitive load below SRF.
2nd a very low ESR resistive path to load at the audio BW for good dampening factor
3rd high attenuation of the switching rate and 4th the harmonics to avoid heating speaker coil with 100V pulses at PWM rate

The gate capacitance (around 50nC) is too high for the switching frequency I am working with. The comparator didn't have time to completely turn on and off the MOSFET due to that high capacitance.

Comparator needs a high speed buffer with impedance ~100X RdsON of MOSFET e.g. if Rdson is 10mOhm Gate driver needs to be around 1 Ohm. but not exceed gate current. Usually fast Off, slower on uses diode // 10 Ohms

think of all MOSFET Bridge stages as gain in conductance of 10 ~100 even though near zero current after switching. Much like Bipolar switches only have a current gain of 10~50 when saturated. This will eliminate slew rate problems but require more stages carefully selected. Final stage should lowest RdsOn you can afford. These are my design methods just for your consideration.

Then you can go back to 100kHz if you follow my reasoning.

Something interesting happens: with the high gate capacitance transistors they didn't even heat a lot, just a bit,

You will find Ciss increases on all MOSFETS as RdsON reduces. This mandates the need to have low impedance gate driver 10~100x higher than RdsOn depending on speed requirements.

I don't own a oscilloscope so everything I find out is thinking about possibilities and discarding some once I reach a reasonable cause for each problem.

I've seen that many designers use both N channel mosfet instead of a complementary pair. Why is it like that? Are P channel mosfets good enough at switching? Should I use this method?

You will learn faster to make better designs with a scope even a $200 scope. It's part of your education. 100MHz min.

N type are lower RdsON by physics but require Bootstrap gate voltage from CR//C from lowside PWM since high side gate must be higher than Vdd

understand?

 

[BrunoARG]

Thank you for your response.

Does it matter if I don't use a gate resistor? I know it is likely to oscillate due to wire inductance but switching speed would be improved. I think I will use it anyways because I don't want to take any oscillation risk.

About dual N channel MOSFET output, what's the voltage loss across the upper one? I mean, do I have to turn it on with VCC+Vp being Vp the gate threshold voltage?

I am thinking about buying one, because it will last a lot of time, it's really useful because I can "see" what I am doing and what the circuit is working like. Actually the more convenient oscilloscope I could see on some local stores is about $600, it's a 4 channel, 50MHz, 1GS/s one, the screen is big and has a lot of functions:SELLER LINK
There's one with 100Mhz, 1GSa/s and 2 channels but is $650. It's a bit expensive (due taxes and country politics.....)

Coming back to the topic, is there any circuit that delays the turn on of one transistor so it don't generate a short between the supply for a short period? It's a waste of energy and overheats the transistors.