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The process design kit (PDK) manual for 180 nm ought to tell you that. Have you read it?


I believe in a 180nm CMOS process, μm for NMOS transistors typically ranges from 300 to 500 cm²/V·s


The gate oxide capacitance per unit area Cox=ϵox/tox

ϵox = ϵr⋅ϵ0  ,  ϵr= 3.9 approx.

tox  =  is typically around 4 to 4.5 nm thick


so correct me if I am wrong.


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