balamani
Member level 1
Hi,
This is regarding the SPI interface and XiP (Execute in place) Mode.
1. Do all the SPI serial NOR Flashes support XiP mode?
2. Is there any requirement for a micro processor if it has to be connected to a SPI serial NOR flash with XiP mode support? i.e. let us consider a micro processor which can support SPI flash. If the selected SPI flash supports XiP mode, can the microprocessor communicate with that SPI flash? or the micro processor should have XiP enable feature in its architecture to support such SPI flash?
Please clarify in detail.
This is regarding the SPI interface and XiP (Execute in place) Mode.
1. Do all the SPI serial NOR Flashes support XiP mode?
2. Is there any requirement for a micro processor if it has to be connected to a SPI serial NOR flash with XiP mode support? i.e. let us consider a micro processor which can support SPI flash. If the selected SPI flash supports XiP mode, can the microprocessor communicate with that SPI flash? or the micro processor should have XiP enable feature in its architecture to support such SPI flash?
Please clarify in detail.