Clarification needed-DDR2-Timing calculation

balamani · Nov 19, 2013

Hi

I have attached a file. I seek your assistance to clarify my query regarding DDR2 timing calculation when Zero Delay buffer is in the clock path.

marce · Nov 19, 2013

Never seen a buffer added to clock on any DDR2 layout, all signals have some from an FPGA, Northbridge processor directly so cant comment. If the buffer is a true zero delay(! HOW) then both trace lengths have to be catered for.

Clarification needed-DDR2-Timing calculation

balamani

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marce

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Clarification needed-DDR2-Timing calculation

balamani

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marce

Advanced Member level 5

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