Clarification needed-DDR2-Timing calculation

[balamani]

Hi

I have attached a file. I seek your assistance to clarify my query regarding DDR2 timing calculation when Zero Delay buffer is in the clock path.

 

[marce]

Never seen a buffer added to clock on any DDR2 layout, all signals have some from an FPGA, Northbridge processor directly so cant comment. If the buffer is a true zero delay(! HOW) then both trace lengths have to be catered for.