I have a question regarding keeping the length of line from an IC to FPGA the same. I want 4 different traces to be almost exactly the same length.
I am using the circular typed trace to make up the same length between each line.
Here is my example, my questionis is, is this kind of trace acceptable for parallel data line? Thank you.
That's exactly what it's used for, when you want all the bits in a bus to arrive at the same time. You might also want to consider inductive effects, depending on your data speed.
Something else to consider: in Xilinx Virtex parts (and probably others) you can compensate for trace delays internally with a programmable delay on each pin so you don't have to worry about the traces so much.