circuit view of a vhdl code

[ranjbar_7]

hi

i need a circuit view of my vhdl code but i dont know how to get to it xilinx ISE gives me a rtl view i need somthing lke this for my vhdl cod

 

[ishailesh]

hi

i need a circuit view of my vhdl code but i dont know how to get to it xilinx ISE gives me a rtl view i need somthing lke this for my vhdl cod

When designing digital integrated circuits with a hardware description language, the designs are usually engineered at a higher level of abstraction than transistor level (logic families) or logic gate level. In HDLs the designer declares the registers, and describes the combination logic by using constructs that are familiar from programming languages such as if-then-else and arithmetic operations.This Register-transfer level refers to the fact that RTL focuses on describing the flow of signals between registers.

An RTL description is usually converted to a gate-level description of the circuit by a logic synthesis tool. The synthesis results are then used by placement and routing tools to create a physical layout. While logic simulation tools may use a design's RTL description to verify for its correctness.
But i guess these two features are missing in Xilinix ISE.